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<title>pm24.git, branch v2.6.36-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>https://git.kobert.dev/pm24.git/atom/?h=v2.6.36-rc2</id>
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<updated>2010-08-23T00:43:29Z</updated>
<entry>
<title>Linux 2.6.36-rc2</title>
<updated>2010-08-23T00:43:29Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-08-23T00:43:29Z</published>
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<id>urn:sha1:76be97c1fc945db08aae1f1b746012662d643e97</id>
<content type='text'>
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<entry>
<title>Merge branch 'kvm-updates/2.6.36' of git://git.kernel.org/pub/scm/virt/kvm/kvm</title>
<updated>2010-08-22T18:27:36Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-08-22T18:27:36Z</published>
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<id>urn:sha1:3dc8d7f07e7496c0c6702e7e4b1acc179fa94019</id>
<content type='text'>
* 'kvm-updates/2.6.36' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: PIT: free irq source id in handling error path
  KVM: destroy workqueue on kvm_create_pit() failures
  KVM: fix poison overwritten caused by using wrong xstate size
</content>
</entry>
<entry>
<title>Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel</title>
<updated>2010-08-22T18:03:27Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-08-22T18:03:27Z</published>
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<id>urn:sha1:4238a417a91643e1162a98770288f630e37f0484</id>
<content type='text'>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (58 commits)
  drm/i915,intel_agp: Add support for Sandybridge D0
  drm/i915: fix render pipe control notify on sandybridge
  agp/intel: set 40-bit dma mask on Sandybridge
  drm/i915: Remove the conflicting BUG_ON()
  drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/
  drm/i915/suspend: Flush register writes before busy-waiting.
  i915: disable DAC on Ironlake also when doing CRT load detection.
  drm/i915: wait for actual vblank, not just 20ms
  drm/i915: make sure eDP PLL is enabled at the right time
  drm/i915: fix VGA plane disable for Ironlake+
  drm/i915: eDP mode set sequence corrections
  drm/i915: add panel reset workaround
  drm/i915: Enable RC6 on Ironlake.
  drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode.
  drm/i915: Set up a render context on Ironlake
  drm/i915 invalidate indirect state pointers at end of ring exec
  drm/i915: Wake-up wait_request() from elapsed hang-check (v2)
  drm/i915: Apply i830 errata for cursor alignment
  drm/i915: Only update i845/i865 CURBASE when disabled (v2)
  drm/i915: FBC is updated within set_base() so remove second call in mode_set()
  ...
</content>
</entry>
<entry>
<title>Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg/slab-2.6</title>
<updated>2010-08-22T17:08:52Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-08-22T17:08:52Z</published>
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<id>urn:sha1:bc584c5107bfd97e2aa41c798e3b213bcdd4eae7</id>
<content type='text'>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg/slab-2.6:
  slab: fix object alignment
  slub: add missing __percpu markup in mm/slub_def.h
</content>
</entry>
<entry>
<title>Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ryusuke/nilfs2</title>
<updated>2010-08-22T16:44:47Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2010-08-22T16:44:47Z</published>
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<id>urn:sha1:a28e0852d45e65d9edf249c36e432b5e0a80f01d</id>
<content type='text'>
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ryusuke/nilfs2:
  nilfs2: wait for discard to finish
</content>
</entry>
<entry>
<title>drm/i915,intel_agp: Add support for Sandybridge D0</title>
<updated>2010-08-22T06:29:03Z</updated>
<author>
<name>Zhenyu Wang</name>
<email>zhenyuw@linux.intel.com</email>
</author>
<published>2010-08-19T01:46:16Z</published>
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<id>urn:sha1:4fefe435626758b14e6c05d2a5f8d71a997c0ad6</id>
<content type='text'>
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
</content>
</entry>
<entry>
<title>drm/i915: fix render pipe control notify on sandybridge</title>
<updated>2010-08-22T06:28:54Z</updated>
<author>
<name>Zhenyu Wang</name>
<email>zhenyuw@linux.intel.com</email>
</author>
<published>2010-08-19T01:46:15Z</published>
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<id>urn:sha1:3fdef0205e69b80c4219f14b834cb85eb719039f</id>
<content type='text'>
This one is missed in last pipe control fix for sandybridge,
that really unmask interrupt bit for notify in render engine IMR.

Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
</content>
</entry>
<entry>
<title>agp/intel: set 40-bit dma mask on Sandybridge</title>
<updated>2010-08-22T06:24:50Z</updated>
<author>
<name>Zhenyu Wang</name>
<email>zhenyuw@linux.intel.com</email>
</author>
<published>2010-08-19T01:46:13Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=877fdacf8291d7627f339885b5ae52c2f6061734'/>
<id>urn:sha1:877fdacf8291d7627f339885b5ae52c2f6061734</id>
<content type='text'>
Signed-off-by: Zhenyu Wang &lt;zhenyuw@linux.intel.com&gt;
Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
</content>
</entry>
<entry>
<title>drm/i915: Remove the conflicting BUG_ON()</title>
<updated>2010-08-22T06:21:13Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2010-08-15T09:52:34Z</published>
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<id>urn:sha1:156dadc180a1bd3a25d644ee6c361afc465ccd0e</id>
<content type='text'>
We now attempt to free "active" objects following a GPU hang as either
the GPU will be reset or the hang is permenant. In either case, the GPU
writes will not be flushed to main memory and it should be safe to
return that memory back to the system.

The BUG_ON(active) is thus overkill and can erroneously fire after a
EIO.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
</content>
</entry>
<entry>
<title>drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/</title>
<updated>2010-08-22T06:20:21Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2010-08-14T13:41:23Z</published>
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<id>urn:sha1:90eb77baaea35c591bd324b31e9eac032bd603c9</id>
<content type='text'>
For the shared paths on the next generation chipsets.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Signed-off-by: Eric Anholt &lt;eric@anholt.net&gt;
</content>
</entry>
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