pm24.git/Documentation/devicetree/bindings/nds32, branch master

nds32: Remove the architecture

2022-03-07T12:54:59Z

The nds32 architecture, also known as AndeStar V3, is a custom 32-bit RISC target designed by Andes Technologies. Support was added to the kernel in 2016 as the replacement RISC-V based V5 processors were already announced, and maintained by (current or former) Andes employees. As explained by Alan Kao, new customers are now all using RISC-V, and all known nds32 users are already on longterm stable kernels provided by Andes, with no development work going into mainline support any more. While the port is still in a reasonably good shape, it only gets worse over time without active maintainers, so it seems best to remove it before it becomes unusable. As always, if it turns out that there are mainline users after all, and they volunteer to maintain the port in the future, the removal can be reverted. Link: https://lore.kernel.org/linux-mm/YhdWNLUhk+x9RAzU@yamatobi.andestech.com/ Link: https://lore.kernel.org/lkml/20220302065213.82702-1-alankao@andestech.com/ Link: https://www.andestech.com/en/products-solutions/andestar-architecture/ Signed-off-by: Alan Kao [arnd: rewrite changelog to provide more background] Signed-off-by: Arnd Bergmann

dt-bindings: nds32 SoC Bindings

2018-02-22T02:44:36Z

This patch adds nds32 SoC(AE3XX and AG101P) binding documents. Signed-off-by: Greentime Hu Reviewed-by: Rob Herring Acked-by: Arnd Bergmann

dt-bindings: nds32 L2 cache controller Bindings

2018-02-22T02:44:36Z

This patch adds nds32 L2 cache controller binding documents. Signed-off-by: Greentime Hu Reviewed-by: Rob Herring Acked-by: Arnd Bergmann

dt-bindings: nds32 CPU Bindings

2018-02-22T02:44:35Z

This patch adds nds32 CPU binding documents. Signed-off-by: Vincent Chen Signed-off-by: Rick Chen Signed-off-by: Zong Li Signed-off-by: Greentime Hu Reviewed-by: Rob Herring