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<updated>2024-11-14T22:52:26Z</updated>
<entry>
<title>dt-bindings: soc: mobileye: set `#clock-cells = &lt;1&gt;` for all compatibles</title>
<updated>2024-11-14T22:52:26Z</updated>
<author>
<name>Théo Lebrun</name>
<email>theo.lebrun@bootlin.com</email>
</author>
<published>2024-11-06T16:03:52Z</published>
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<content type='text'>
Some compatibles expose a single clock. For those, we used to let them
using `#clock-cells = &lt;0&gt;` (ie &lt;&amp;olb&gt; reference rather than &lt;&amp;olb 0&gt;).

Switch away from that: enforce a cell for all compatibles. This is more
straight forward, and avoids devicetree changes whenever a compatible
goes from exposing a single clock to multiple ones. Also, dt-bindings
get simpler.

*This is an ABI break*. Change it while EyeQ5 platform support is at its
infancy, without any user. More clocks might hide in each OLB as some
registers are still unknown.

Signed-off-by: Théo Lebrun &lt;theo.lebrun@bootlin.com&gt;
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-1-84cfefb3f485@bootlin.com
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: soc: mobileye: add EyeQ OLB system controller</title>
<updated>2024-07-03T15:15:47Z</updated>
<author>
<name>Théo Lebrun</name>
<email>theo.lebrun@bootlin.com</email>
</author>
<published>2024-06-28T16:11:50Z</published>
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<content type='text'>
Add documentation to describe the "Other Logic Block" system-controller.
It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have
a single instance, whereas EyeQ6H has seven named instances.

Features provided are:
 - Clocks, children to main crystal. Some PLLs and divider clocks.
 - Resets. Some instances DO NOT have reset.
 - Pinctrl. Only EyeQ5 has such feature.

Those are NOT the only features exposed in OLB system-controllers! Many
individual registers, related to IP block integration, can be found.
Additional features will be exposed over time.

We simplify devicetree phandles to OLB in two ways:

 - Compatibles exposing a single clock do not ask for a index argument.
   This means we use EyeQ6H OLB south (it has four clocks):

      clocks = &lt;&amp;olb_south EQ6HC_SOUTH_PLL_PER&gt;;

   But use EyeQ6H OLB east (it has one clock):

      clocks = &lt;&amp;olb_east&gt;;

 - Compatibles exposing a single reset domain do not ask for a domain
   index, only a reset index.
   This means we use EyeQ5 OLB (it has three domains):

     resets = &lt;&amp;olb 0 10&gt;;

   But use EyeQ6H west reset (it has one domain):

      resets = &lt;&amp;olb_west 3&gt;;

About pinctrl subnodes: all pins have two functionality, either GPIO or
something-else. The latter is pin dependent, we express constraints
using many if-then.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Théo Lebrun &lt;theo.lebrun@bootlin.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
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