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<title>pm24.git/arch/mips/kernel, branch rust-6.13</title>
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<id>https://git.kobert.dev/pm24.git/atom/arch/mips/kernel?h=rust-6.13</id>
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<updated>2024-09-17T04:56:31Z</updated>
<entry>
<title>Merge tag 'smp-core-2024-09-16' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2024-09-17T04:56:31Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-09-17T04:56:31Z</published>
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<id>urn:sha1:97e17c08a428b17531894b59990d6b9ff3e95eab</id>
<content type='text'>
Pull CPU hotplug updates from Thomas Gleixner:

 - Prepare the core for supporting parallel hotplug on loongarch

 - A small set of cleanups and enhancements

* tag 'smp-core-2024-09-16' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  smp: Mark smp_prepare_boot_cpu() __init
  cpu: Fix W=1 build kernel-doc warning
  cpu/hotplug: Provide weak fallback for arch_cpuhp_init_parallel_bringup()
  cpu/hotplug: Make HOTPLUG_PARALLEL independent of HOTPLUG_SMT
</content>
</entry>
<entry>
<title>Merge tag 'mips_6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2024-09-16T04:53:14Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-09-16T04:53:14Z</published>
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<id>urn:sha1:8617d7d6298f54dfef4038281863270b5864fe83</id>
<content type='text'>
Pull MIPS updates from Thomas Bogendoerfer:

 - use devm_clk_get_enabled() helper

 - prototype fixes

 - cleanup unused stuff

* tag 'mips_6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  mips: Remove posix_types.h include from sigcontext.h
  bus: bt1-apb: change to use devm_clk_get_enabled() helper
  bus: bt1-axi: change to use devm_clk_get_enabled() helper
  MIPS: dec: prom: Remove unused unregister_prom_console() declaration
  MIPS: Remove unused mips_display/_scroll_message() declarations
  MIPS: Remove unused declarations in asm/cmp.h
  MIPS: MT: Remove unused function mips_mt_regdump()
  mips/jazz: remove unused jazz_handle_int() declaration
  MIPS: Remove unused function dump_au1000_dma_channel() in dma.c
  MIPS: ralink: Fix missing `get_c0_perfcount_int` prototype
  MIPS: ralink: Fix missing `plat_time_init` prototype
</content>
</entry>
<entry>
<title>smp: Mark smp_prepare_boot_cpu() __init</title>
<updated>2024-09-08T14:01:10Z</updated>
<author>
<name>Bibo Mao</name>
<email>maobibo@loongson.cn</email>
</author>
<published>2024-09-07T08:27:20Z</published>
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<id>urn:sha1:1d07085402d122f223bda3f8b72bea37a46ee0c9</id>
<content type='text'>
smp_prepare_boot_cpu() is only called during boot, hence mark it as
__init.

Signed-off-by: Bibo Mao &lt;maobibo@loongson.cn&gt;
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
Link: https://lore.kernel.org/all/20240907082720.452148-1-maobibo@loongson.cn
</content>
</entry>
<entry>
<title>MIPS: MT: Remove unused function mips_mt_regdump()</title>
<updated>2024-08-29T08:41:36Z</updated>
<author>
<name>Gaosheng Cui</name>
<email>cuigaosheng1@huawei.com</email>
</author>
<published>2024-08-14T10:39:33Z</published>
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<id>urn:sha1:3fd19664c3bd50dc479ff444e43787439074458a</id>
<content type='text'>
The mips_mt_regdump() has not been used since
commit b633648c5ad3 ("MIPS: MT: Remove SMTC support"), so remove it.

Signed-off-by: Gaosheng Cui &lt;cuigaosheng1@huawei.com&gt;
Reviewed-by: Ricardo B. Marliere &lt;ricardo@marliere.net&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>Revert "MIPS: csrc-r4k: Apply verification clocksource flags"</title>
<updated>2024-08-25T22:26:30Z</updated>
<author>
<name>Guenter Roeck</name>
<email>linux@roeck-us.net</email>
</author>
<published>2024-08-06T01:13:41Z</published>
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<id>urn:sha1:5a4c785905fd9361d067127b42564c08893f2a6f</id>
<content type='text'>
This reverts commit 7190401fc56fb5f02ee3d04476778ab000bbaf32.

Verifying the clock source sometimes deems the MIPS clock
to be unstable, at least in qemu.

clocksource: timekeeping watchdog on CPU0: Marking clocksource 'MIPS' as unstable because the skew is too large:
clocksource:                       'jiffies' wd_nsec: 500000000 wd_now: ffff8bde wd_last: ffff8bac mask: ffffffff
clocksource:                       'MIPS' cs_nsec: 940634468 cs_now: 310181c4 cs_last: 28090a09 mask: ffffffff
clocksource:                       Clocksource 'MIPS' skewed 440634468 ns (440 ms) over watchdog 'jiffies' interval of 500000000 ns (500 ms)
clocksource:                       'MIPS' is current clocksource.

If this happens, network interfaces fail to come online.

Signed-off-by: Guenter Roeck &lt;linux@roeck-us.net&gt;
</content>
</entry>
<entry>
<title>MIPS: cevt-r4k: Don't call get_c0_compare_int if timer irq is installed</title>
<updated>2024-08-20T08:36:52Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-08-13T09:59:08Z</published>
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<id>urn:sha1:50f2b98dc83de7809a5c5bf0ccf9af2e75c37c13</id>
<content type='text'>
This avoids warning:

[    0.118053] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:283

Caused by get_c0_compare_int on secondary CPU.

We also skipped saving IRQ number to struct clock_event_device *cd as
it's never used by clockevent core, as per comments it's only meant
for "non CPU local devices".

Reported-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Closes: https://lore.kernel.org/linux-mips/6szkkqxpsw26zajwysdrwplpjvhl5abpnmxgu2xuj3dkzjnvsf@4daqrz4mf44k/
Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Reviewed-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Tested-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson64: Set timer mode in cpu-probe</title>
<updated>2024-08-08T16:17:43Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-07-23T09:15:44Z</published>
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<id>urn:sha1:1cb6ab446424649f03c82334634360c2e3043684</id>
<content type='text'>
Loongson64 C and G processors have EXTIMER feature which
is conflicting with CP0 counter.

Although the processor resets in EXTIMER disabled &amp; INTIMER
enabled mode, which is compatible with MIPS CP0 compare, firmware
may attempt to enable EXTIMER and interfere CP0 compare.

Set timer mode back to MIPS compatible mode to fix booting on
systems with such firmware before we have an actual driver for
EXTIMER.

Cc: stable@vger.kernel.org
Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'mips_6.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2024-07-25T19:41:53Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-07-25T19:41:53Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=28e7241cb857415fbc8d8d962e2b423c3842e9f9'/>
<id>urn:sha1:28e7241cb857415fbc8d8d962e2b423c3842e9f9</id>
<content type='text'>
Pull MIPS updates from Thomas Bogendoerfer:

 - Use improved timer sync for Loongson64

 - Fix address of GCR_ACCESS register

 - Add missing MODULE_DESCRIPTION

* tag 'mips_6.11_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  mips: sibyte: add missing MODULE_DESCRIPTION() macro
  MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later
  MIPS: Loongson64: Switch to SYNC_R4K
</content>
</entry>
<entry>
<title>MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later</title>
<updated>2024-07-23T07:30:13Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2024-07-22T13:15:39Z</published>
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<id>urn:sha1:a263e5f309f32301e1f3ad113293f4e68a82a646</id>
<content type='text'>
When the CM block migrated from CM2.5 to CM3.0, the address offset for
the Global CSR Access Privilege register was modified. We saw this in
the "MIPS64 I6500 Multiprocessing System Programmer's Guide," it is
stated that "the Global CSR Access Privilege register is located at
offset 0x0120" in section 5.4. It is at least the same for I6400.

This fix allows to use the VP cores in SMP mode if the reset values
were modified by the bootloader.

Based on the work of Vladimir Kondratiev
&lt;vladimir.kondratiev@mobileye.com&gt; and the feedback from Jiaxun Yang
&lt;jiaxun.yang@flygoat.com&gt;.

Fixes: 197e89e0984a ("MIPS: mips-cm: Implement mips_cm_revision")
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2024-07-20T16:03:36Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-07-20T16:03:36Z</published>
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<id>urn:sha1:d2be38b9a5514dbc7dc0c96a2a7f619fcddce00d</id>
<content type='text'>
Pull MIPS updates from Thomas Bogendoerfer:

 - add support for Realtek RTL9302C

 - add support for Mobileye EyeQ6H

 - add support for Mobileye EyeQ OLB system controller

 - improve r4k clocksource

 - add mode for emulating ieee754 NAN2008

 - rework for BMIPS CBR address handling

 - fixes for Loongson 2K1000

 - defconfig updates

 - cleanups and fixes

* tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits)
  MIPS: config: Add ip30_defconfig
  MIPS: config: lemote2f: Regenerate defconfig
  MIPS: config: generic: Add board-litex
  MIPS: config: Enable MSA and virtualization for MIPS64R6
  MIPS: Fix fallback march for SB1
  mips: dts: realtek: Add RTL9302C board
  mips: generic: add fdt fixup for Realtek reference board
  mips: select REALTEK_OTTO_TIMER for Realtek platforms
  dt-bindings: interrupt-controller: realtek,rtl-intc: Add rtl9300-intc
  dt-bindings: mips: realtek: Add rtl930x-soc compatible
  dt-bindings: vendor-prefixes: Add Cameo Communications
  mips: dts: realtek: add device_type property to cpu node
  mips: dts: realtek: use "serial" instead of "uart" in node name
  MIPS: Implement ieee754 NAN2008 emulation mode
  MIPS: lantiq: improve USB initialization
  MIPS: GIC: Generate redirect block accessors
  MIPS: CPS: Add a couple of multi-cluster utility functions
  MIPS: Octeron: remove source file executable bit
  MAINTAINERS: Mobileye: add OLB drivers and dt-bindings
  MIPS: mobileye: eyeq5: add OLB system-controller node
  ...
</content>
</entry>
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