pm24.git/arch/xtensa/kernel/head.S, branch rust-6.8

xtensa: use register window specific opcodes only when present

2021-10-19T05:19:35Z

xtensa core may be configured without register windows support, don't use register window specific opcodes in that case. Use window register specific opcodes to initialize hardware or reset core to a known state regardless of the chosen ABI. Signed-off-by: Max Filippov

xtensa: implement call0 ABI support in assembly

2021-10-19T05:19:35Z

Replace hardcoded register and opcode names with ABI-agnostic macros. Add register save/restore code where necessary. Conditionalize windowed only or call0 only code. Add stack initialization matching _switch_to epilogue to copy_thread. Signed-off-by: Max Filippov

xtensa: Couple of typo fixes

2021-04-04T22:39:04Z

s/contans/contains/ s/desination/destination/ Signed-off-by: Bhaskar Chowdhury Message-Id: <20210325040832.26018-1-unixbhaskar@gmail.com> Signed-off-by: Max Filippov

xtensa: add XIP kernel support

2019-11-26T19:33:38Z

XIP (eXecute In Place) kernel image is the image that can be run directly from ROM, using RAM only for writable data. XIP xtensa kernel differs from regular xtensa kernel in the following ways: - it has exception/IRQ vectors merged into text section. No vectors relocation takes place at kernel startup. - .data/.bss location must be specified in the kernel configuration, its content is copied there in the _startup function. - .init.text is merged with the rest of text and is executed from ROM. - when MMU is used the virtual address where the kernel will be mapped must be specified in the kernel configuration. It may be in the KSEG or in the KIO, __pa macro is adjusted to be able to handle both. Signed-off-by: Max Filippov

xtensa: fix section name for start_info

2019-10-21T06:48:29Z

.data.init.refok has been removed from the kernel long ago, replaced with __REFDATA. Fix start_info definition. Signed-off-by: Max Filippov

xtensa: clean up PS_WOE_BIT usage

2019-09-01T20:11:57Z

PS_WOE_BIT is mainly used to generate PS.WOE mask in the code. Introduce PS_WOE_MASK macro and use it instead. Signed-off-by: Max Filippov

xtensa: SMP: fix secondary CPU initialization

2019-01-26T10:02:13Z

- add missing memory barriers to the secondary CPU synchronization spin loops; add comment to the matching memory barrier in the boot_secondary and __cpu_die functions; - use READ_ONCE/WRITE_ONCE to access cpu_start_id/cpu_start_ccount instead of reading/writing them directly; - re-initialize cpu_running every time before starting secondary CPU to flush possible previous CPU startup results. Signed-off-by: Max Filippov

xtensa: don't use l32r opcode directly

2018-12-05T20:53:07Z

xtensa assembler is capable of representing register loads with either movi + addmi, l32r or const16, depending on the core configuration. Don't use '.literal' and 'l32r' directly in the code, use 'movi' and let the assembler relax them. Signed-off-by: Max Filippov

xtensa: fix boot parameters address translation

2018-11-14T08:15:32Z

The bootloader may pass physical address of the boot parameters structure to the MMUv3 kernel in the register a2. Code in the _SetupMMU block in the arch/xtensa/kernel/head.S is supposed to map that physical address to the virtual address in the configured virtual memory layout. This code haven't been updated when additional 256+256 and 512+512 memory layouts were introduced and it may produce wrong addresses when used with these layouts. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov

xtensa: rework noMMU cache attributes initialization

2018-08-14T03:08:19Z

Marking default memory region as cached is not always sufficient and is not flexible. Allow specifying cache attributes for the whole memory address space with new config entry MEMMAP_CACHEATTR. Apply it after cache initialization. Signed-off-by: Max Filippov