pm24.git/drivers/clk/imx, branch master

clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()

2024-11-05T10:07:59Z

If device_link_add() fails, it returns NULL pointer not ERR_PTR(), replace IS_ERR() with NULL pointer check, and return -EINVAL. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Signed-off-by: Yang Yingliang Reviewed-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20241026112452.1523-1-yangyingliang@huaweicloud.com Signed-off-by: Abel Vesa

clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore

2024-11-05T10:02:23Z

On i.MX8QM, HDMI LPCG clocks operation needs SCU clock "hdmi_ipg_clk" to be ON. While during noirq suspend phase, "hdmi_ipg_clk" is disabled by HDMI IRQ STEER driver, so SError will be triggered when accessing the HDMI LPCG registers. Skip all HDMI LPCG clocks save/restore to avoid SError during system suspend/resume, it will NOT introduce additional power consumption as their parent clock is disabled when suspend. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-5-89152574d1d7@nxp.com Signed-off-by: Abel Vesa

clk: imx: clk-scu: fix clk enable state save and restore

2024-11-05T10:02:22Z

The scu clk_ops only inplements prepare() and unprepare() callback. Saving the clock state during suspend by checking clk_hw_is_enabled() is not safe as it's possible that some device drivers may only disable the clocks without unprepare. Then the state retention will not work for such clocks. Fixing it by checking clk_hw_is_prepared() which is more reasonable and safe. Fixes: d0409631f466 ("clk: imx: scu: add suspend/resume support") Reviewed-by: Peng Fan Tested-by: Carlos Song Signed-off-by: Dong Aisheng Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-4-89152574d1d7@nxp.com Signed-off-by: Abel Vesa

clk: imx: fracn-gppll: fix pll power up

2024-11-05T10:02:22Z

To i.MX93 which features dual Cortex-A55 cores and DSU, when using writel_relaxed to write value to PLL registers, the value might be buffered. To make sure the value has been written into the hardware, using readl to read back the register could achieve the goal. current PLL power up flow can be simplified as below: 1. writel_relaxed to set the PLL POWERUP bit; 2. readl_poll_timeout to check the PLL lock bit: a). timeout = ktime_add_us(ktime_get(), timeout_us); b). readl the pll the lock reg; c). check if the pll lock bit ready d). check if timeout But in some corner cases, both the write in step 1 and read in step 2 will be blocked by other bus transaction in the SoC for a long time, saying the value into real hardware is just before step b). That means the timeout counting has begins for quite sometime since step a), but value still not written into real hardware until bus released just at a point before step b). Then there maybe chances that the pll lock bit is not ready when readl done but the timeout happens. readl_poll_timeout will err return due to timeout. To avoid such unexpected failure, read back the reg to make sure the write has been done in HW reg. So use readl after writel_relaxed to fix the issue. Since we are here, to avoid udelay to run before writel_relaxed, use readl before udelay. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-3-89152574d1d7@nxp.com Signed-off-by: Abel Vesa

clk: imx: fracn-gppll: correct PLL initialization flow

2024-11-05T10:02:21Z

Per i.MX93 Reference Mannual 22.4 Initialization information 1. Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI] as per Integer mode. 2. Wait for 5 μs. 3. Program the following field in CTRL register. Set CTRL[POWERUP] to 1'b1 to enable PLL block. 4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK] is 1'b1 and pll_lock output signal is 1'b1. 5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock. So move the CLKMUX_EN operation after PLL locked. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-2-89152574d1d7@nxp.com Signed-off-by: Abel Vesa

clk: imx: lpcg-scu: SW workaround for errata (e10858)

2024-11-05T10:02:20Z

Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by at least 4 cycles of the gated clock. See https://www.nxp.com.cn/docs/en/errata/IMX8_1N94W.pdf The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Fixes: 2f77296d3df9 ("clk: imx: add lpcg clock support") Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-1-89152574d1d7@nxp.com Signed-off-by: Abel Vesa

clk: imx: add i.MX91 clk

2024-10-23T19:48:31Z

Reuse i.MX93 clk driver for i.MX91, because i.MX91 reuses the Clock Control Module from i.MX93, with only a few clocks removed and a few clocks added. For clocks specific to i.MX93 use PLAT_IMX93 to flag them, for clocks specific to i.MX91, use PLAT_IMX91 to flag them. Others are shared by both. Signed-off-by: Pengfei Li Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20241023184651.381265-5-pengfei.li_1@nxp.com Signed-off-by: Abel Vesa

clk: imx93: Move IMX93_CLK_END macro to clk driver

2024-10-23T19:48:28Z

IMX93_CLK_END was previously defined in imx93-clock.h to indicate the number of clocks. However, it is not part of the ABI. For starters it does no really appear in DTS. But what's more important - new clocks are described later, which contradicts this define in binding header. So move this macro to clock driver. Signed-off-by: Pengfei Li Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20241023184651.381265-2-pengfei.li_1@nxp.com Signed-off-by: Abel Vesa

clk: imx95-blk-ctl: Add one clock gate for HSIO block

2024-10-22T14:21:13Z

CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out enable/disable. Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock out gate. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/1728977644-8207-3-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Abel Vesa

clk: Switch back to struct platform_driver::remove()

2024-09-21T21:12:05Z

After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com Acked-by: Geert Uytterhoeven # renesas Signed-off-by: Stephen Boyd