pm24.git/drivers/clk/mediatek/Makefile, branch master

clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers

2024-11-14T20:52:14Z

Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana Link: https://lore.kernel.org/r/20241106111402.200940-3-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd

clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers

2024-10-17T19:24:35Z

Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg clock and reset controllers. These provide the base clocks and resets on the platform, enough to bring up all essential blocks including PWRAP, MSDC and peripherals (UART, I2C, SPI). Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241017071708.38663-3-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd

clk: mediatek: add drivers for MT7988 SoC

2024-01-03T23:57:02Z

Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are typical MediaTek designs. Also add driver for XFIPLL clock generating the 156.25MHz clock for the XFI SerDes. It needs an undocumented software workaround and has an unknown internal design. Signed-off-by: Sam Shih Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org [sboyd@kernel.org: Add module license to infracfg file] Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 adsp clock support

2023-03-31T18:51:22Z

Add MT8188 adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by: Garmin.Chang Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-20-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 imp i2c wrapper clock support

2023-03-31T18:51:22Z

Add MT8188 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by: Garmin.Chang Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-19-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 wpesys clock support

2023-03-31T18:51:22Z

Add MT8188 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Garmin.Chang Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-18-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 vppsys1 clock support

2023-03-31T18:51:22Z

Add MT8188 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang Reviewed-by: Matthias Brugger Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-17-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 vppsys0 clock support

2023-03-31T18:51:22Z

Add MT8188 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Garmin.Chang Reviewed-by: Matthias Brugger Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-16-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 vencsys clock support

2023-03-31T18:51:21Z

Add MT8188 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by: Garmin.Chang Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-15-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd

clk: mediatek: Add MT8188 vdosys1 clock support

2023-03-31T18:51:21Z

Add MT8188 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Garmin.Chang Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230331123621.16167-14-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd