pm24.git/drivers/clk/starfive, branch rust-6.12

clk: starfive: jh7110-vout: Convert to platform remove callback returning void

2024-03-08T23:18:36Z

The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/90054b8b2e118bc04ec37e044d0ac518bb177cf4.1709721042.git.u.kleine-koenig@pengutronix.de Reviewed-by: Hal Feng Signed-off-by: Stephen Boyd

clk: starfive: jh7110-isp: Convert to platform remove callback returning void

2024-03-08T23:18:36Z

The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/312ec7052c4e327c0b365e167a8e86b406cb7dfa.1709721042.git.u.kleine-koenig@pengutronix.de Reviewed-by: Hal Feng Signed-off-by: Stephen Boyd

clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx

2024-01-03T23:51:58Z

This is needed by the dwmac-starfive ethernet driver to set the clock for 1000, 100 and 10 Mbps links properly. Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Reviewed-by: Jacob Keller Link: https://lore.kernel.org/r/20231219232442.2460166-3-cristian.ciocaltea@collabora.com Signed-off-by: Stephen Boyd

clk: starfive: Add flags argument to JH71X0__MUX macro

2024-01-03T23:51:55Z

This flag is needed to add the CLK_SET_RATE_PARENT flag on the gmac_tx clock on the JH7100, which in turn is needed by the dwmac-starfive driver to set the clock properly for 1000, 100 and 10 Mbps links. This change was mostly made using coccinelle: @ match @ expression idx, name, nparents; @@ JH71X0__MUX( -idx, name, nparents, +idx, name, 0, nparents, ...) Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Reviewed-by: Jacob Keller Link: https://lore.kernel.org/r/20231219232442.2460166-2-cristian.ciocaltea@collabora.com Signed-off-by: Stephen Boyd

Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next

2023-08-30T21:37:45Z

- Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes

clk: Explicitly include correct DT includes

2023-07-19T20:13:16Z

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen Acked-by: Krzysztof Kozlowski # samsung Acked-by: Heiko Stuebner #rockchip Acked-by: Chanwoo Choi Acked-by: Geert Uytterhoeven Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Luca Ceresoli # versaclock5 Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa #imx Signed-off-by: Stephen Boyd

clk: starfive: Simplify .determine_rate()

2023-07-19T19:50:42Z

jh71x0_clk_mux_determine_rate() is the same as __clk_mux_determine_rate(), so use the latter to save some LoC. Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/085541814ebe2543cb7e8a31004c0da3e7d5b6eb.1688760111.git.christophe.jaillet@wanadoo.fr Reviewed-by: Emil Renner Berthing Signed-off-by: Stephen Boyd

clk: starfive: Add StarFive JH7110 Video-Output clock driver

2023-07-19T17:08:05Z

Add driver for the StarFive JH7110 Video-Output clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Acked-by: Palmer Dabbelt Reviewed-by: Emil Renner Berthing Reviewed-by: Hal Feng Signed-off-by: Xingyu Wu Signed-off-by: Conor Dooley

clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver

2023-07-19T17:08:05Z

Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG before registering. Acked-by: Palmer Dabbelt Reviewed-by: Emil Renner Berthing Reviewed-by: Hal Feng Signed-off-by: Xingyu Wu Signed-off-by: Conor Dooley

clk: starfive: Add StarFive JH7110 System-Top-Group clock driver

2023-07-19T17:08:05Z

Add driver for the StarFive JH7110 System-Top-Group clock controller. Acked-by: Palmer Dabbelt Reviewed-by: Hal Feng Co-developed-by: Xingyu Wu Signed-off-by: Xingyu Wu Signed-off-by: Emil Renner Berthing Signed-off-by: Conor Dooley