Unnamed repository; edit this file 'description' to name the repository. https://git.kobert.dev/pm24.git/atom?h=v3.18-rc2 2014-10-15T05:48:18Z 2014-10-15T05:48:18Z Linus Torvalds torvalds@linux-foundation.org 2014-10-15T05:48:18Z urn:sha1:0429fbc0bdc297d64188483ba029a23773ae07b0 Pull percpu consistent-ops changes from Tejun Heo: "Way back, before the current percpu allocator was implemented, static and dynamic percpu memory areas were allocated and handled separately and had their own accessors. The distinction has been gone for many years now; however, the now duplicate two sets of accessors remained with the pointer based ones - this_cpu_*() - evolving various other operations over time. During the process, we also accumulated other inconsistent operations. This pull request contains Christoph's patches to clean up the duplicate accessor situation. __get_cpu_var() uses are replaced with with this_cpu_ptr() and __this_cpu_ptr() with raw_cpu_ptr(). Unfortunately, the former sometimes is tricky thanks to C being a bit messy with the distinction between lvalues and pointers, which led to a rather ugly solution for cpumask_var_t involving the introduction of this_cpu_cpumask_var_ptr(). This converts most of the uses but not all. Christoph will follow up with the remaining conversions in this merge window and hopefully remove the obsolete accessors" * 'for-3.18-consistent-ops' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: (38 commits) irqchip: Properly fetch the per cpu offset percpu: Resolve ambiguities in __get_cpu_var/cpumask_var_t -fix ia64: sn_nodepda cannot be assigned to after this_cpu conversion. Use __this_cpu_write. percpu: Resolve ambiguities in __get_cpu_var/cpumask_var_t Revert "powerpc: Replace __get_cpu_var uses" percpu: Remove __this_cpu_ptr clocksource: Replace __this_cpu_ptr with raw_cpu_ptr sparc: Replace __get_cpu_var uses avr32: Replace __get_cpu_var with __this_cpu_write blackfin: Replace __get_cpu_var uses tile: Use this_cpu_ptr() for hardware counters tile: Replace __get_cpu_var uses powerpc: Replace __get_cpu_var uses alpha: Replace __get_cpu_var ia64: Replace __get_cpu_var uses s390: cio driver &__get_cpu_var replacements s390: Replace __get_cpu_var uses mips: Replace __get_cpu_var uses MIPS: Replace __get_cpu_var uses in FPU emulator. arm: Replace __this_cpu_ptr with raw_cpu_ptr ... 2014-10-09T10:35:05Z Linus Torvalds torvalds@linux-foundation.org 2014-10-09T10:35:05Z urn:sha1:47137c6ba1bcde30215795f9594cea770946456b Pull timer updates from Thomas Gleixner: "Nothing really exciting this time: - a few fixlets in the NOHZ code - a new ARM SoC timer abomination. One should expect that we have enough of them already, but they insist on inventing new ones. - the usual bunch of ARM SoC timer updates. That feels like herding cats" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource: arm_arch_timer: Consolidate arch_timer_evtstrm_enable clocksource: arm_arch_timer: Enable counter access for 32-bit ARM clocksource: arm_arch_timer: Change clocksource name if CP15 unavailable clocksource: sirf: Disable counter before re-setting it clocksource: cadence_ttc: Add support for 32bit mode clocksource: tcb_clksrc: Sanitize IRQ request clocksource: arm_arch_timer: Discard unavailable timers correctly clocksource: vf_pit_timer: Support shutdown mode ARM: meson6: clocksource: Add Meson6 timer support ARM: meson: documentation: Add timer documentation clocksource: sh_tmu: Document r8a7779 binding clocksource: sh_mtu2: Document r7s72100 binding clocksource: sh_cmt: Document SoC specific bindings timerfd: Remove an always true check nohz: Avoid tick's double reprogramming in highres mode nohz: Fix spurious periodic tick behaviour in low-res dynticks mode 2014-10-08T21:37:16Z Linus Torvalds torvalds@linux-foundation.org 2014-10-08T21:37:16Z urn:sha1:8b45bc892e6842115fc87c2b2a3b86a20617606a Pull ARM SoC driver updates from Arnd Bergmann: "These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. Most of the new code is for the Keystone Navigator driver, which is new base support that is going to be needed for their hardware accelerated network driver and other units. Most of the commits are for moving old code around from at91 and omap for things that are done in device drivers nowadays. - at91: move reset, poweroff, memory and clocksource code into drivers directories - socfpga: add edac driver (through arm-soc, as requested by Boris) - omap: move omap-intc code to drivers/irqchip - sunxi: added an RTC driver for sun6i - omap: mailbox driver related changes - keystone: support for the "Navigator" component - versatile: new reboot, led and soc drivers" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (92 commits) bus: arm-ccn: Fix spurious warning message leds: add device tree bindings for register bit LEDs soc: add driver for the ARM RealView power: reset: driver for the Versatile syscon reboot leds: add a driver for syscon-based LEDs drivers/soc: ti: fix build break with modules MAINTAINERS: Add Keystone Multicore Navigator drivers entry soc: ti: add Keystone Navigator DMA support Documentation: dt: soc: add Keystone Navigator DMA bindings soc: ti: add Keystone Navigator QMSS driver Documentation: dt: soc: add Keystone Navigator QMSS bindings rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc rtc: sun6i: Add sun6i RTC driver irqchip: omap-intc: remove unnecessary comments irqchip: omap-intc: correct maximum number or MIR registers irqchip: omap-intc: enable TURBO idle mode irqchip: omap-intc: enable IP protection irqchip: omap-intc: remove unnecesary of_address_to_resource() call irqchip: omap-intc: comment style cleanup irqchip: omap-intc: minor improvement to omap_irq_pending() ... 2014-09-28T23:59:26Z Nathan Lynch nathan_lynch@mentor.com 2014-09-28T23:50:06Z urn:sha1:e1ce5c7adc735ce96a35806ca32ceb78e607a283 The arch_timer_evtstrm_enable hooks in arm and arm64 are substantially similar, the only difference being a CONFIG_COMPAT-conditional section which is relevant only for arm64. Copy the arm64 version to the driver, removing the arch-specific hooks. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> 2014-09-28T23:59:25Z Nathan Lynch nathan_lynch@mentor.com 2014-09-28T23:50:06Z urn:sha1:8b8dde00347ef409b29abd97e5833ffdb4ed7508 The only difference between arm and arm64's implementations of arch_counter_set_user_access is that 32-bit ARM does not enable user access to the virtual counter. We want to enable this access for the 32-bit ARM VDSO, so copy the arm64 version to the driver itself, and remove the arch-specific implementations. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> 2014-09-28T23:59:24Z Nathan Lynch nathan_lynch@mentor.com 2014-09-28T23:50:06Z urn:sha1:423bd69e69f565167ba14e2fe61df76c3c4a0d26 The arm and arm64 VDSOs need CP15 access to the architected counter. If this is unavailable (which is allowed by ARM v7), indicate this by changing the clocksource name to "arch_mem_counter" before registering the clocksource. Suggested by Stephen Boyd. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> 2014-09-28T23:59:24Z Hao Liu Hao.Liu@csr.com 2014-09-28T23:50:06Z urn:sha1:28cf35675a66947b20731f6acbc9d5b131930ce3 According to HW spec, we have to disable the counter before setting it, if we don't this, in pressure test, sometimes the timer might not generate interrupt any more. And this patch also fixes a typo for register set by changing 0x7 to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3. Signed-off-by: Hao Liu <Hao.Liu@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 2014-09-28T23:59:09Z Michal Simek michal.simek@xilinx.com 2014-09-28T23:50:05Z urn:sha1:4e2bec0c327025671c1ec2101660e8fea29d9d89 New TTCs support 32bit mode. Older versions support only 16bit modes. Keep 16bit mode as default and 32bit optional. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 2014-09-28T23:50:05Z Gael Portay gael.portay@gmail.com 2014-09-28T23:50:05Z urn:sha1:2743f1beb0d31be9f59b6fc84f755fb4e173df4d The clock is not unprepared in case of the request IRQ fails. Also update to request_irq. Signed-off-by: Gaël PORTAY <gael.portay@gmail.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> 2014-09-28T23:50:05Z Sudeep Holla sudeep.holla@arm.com 2014-09-28T23:50:05Z urn:sha1:c387f07e6205cc13f57c1def5f885bf0a20e1c2d Currently we wait until both cp15 and mem timers are probed if we have both timer device nodes present in the device tree without checking if the device is actually available. If one of the timer device node present is disabled, the system locks up on the boot as no timer gets registered. This patch adds the check for the availability of the timer device so that unavailable timers are discarded correctly. It also adds the missing of_node_put. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>