<feed xmlns='http://www.w3.org/2005/Atom'>
<title>pm24.git/drivers/clocksource, branch v6.11-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<id>https://git.kobert.dev/pm24.git/atom?h=v6.11-rc2</id>
<link rel='self' href='https://git.kobert.dev/pm24.git/atom?h=v6.11-rc2'/>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/'/>
<updated>2024-07-25T11:53:47Z</updated>
<entry>
<title>of: remove internal arguments from of_property_for_each_u32()</title>
<updated>2024-07-25T11:53:47Z</updated>
<author>
<name>Luca Ceresoli</name>
<email>luca.ceresoli@bootlin.com</email>
</author>
<published>2024-07-24T16:33:06Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=9722c3b66e21ff08aec570d02a97d331087fd70f'/>
<id>urn:sha1:9722c3b66e21ff08aec570d02a97d331087fd70f</id>
<content type='text'>
The of_property_for_each_u32() macro needs five parameters, two of which
are primarily meant as internal variables for the macro itself (in the
for() clause). Yet these two parameters are used by a few drivers, and this
can be considered misuse or at least bad practice.

Now that the kernel uses C11 to build, these two parameters can be avoided
by declaring them internally, thus changing this pattern:

  struct property *prop;
  const __be32 *p;
  u32 val;

  of_property_for_each_u32(np, "xyz", prop, p, val) { ... }

to this:

  u32 val;

  of_property_for_each_u32(np, "xyz", val) { ... }

However two variables cannot be declared in the for clause even with C11,
so declare one struct that contain the two variables we actually need. As
the variables inside this struct are not meant to be used by users of this
macro, give the struct instance the noticeable name "_it" so it is visible
during code reviews, helping to avoid new code to use it directly.

Most usages are trivially converted as they do not use those two
parameters, as expected. The non-trivial cases are:

 - drivers/clk/clk.c, of_clk_get_parent_name(): easily doable anyway
 - drivers/clk/clk-si5351.c, si5351_dt_parse(): this is more complex as the
   checks had to be replicated in a different way, making code more verbose
   and somewhat uglier, but I refrained from a full rework to keep as much
   of the original code untouched having no hardware to test my changes

All the changes have been build tested. The few for which I have the
hardware have been runtime-tested too.

Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt; # drivers/clk/sunxi/clk-simple-gates.c, drivers/clk/sunxi/clk-sun8i-bus-gates.c
Acked-by: Bartosz Golaszewski &lt;bartosz.golaszewski@linaro.org&gt; # drivers/gpio/gpio-brcmstb.c
Acked-by: Nicolas Ferre &lt;nicolas.ferre@microchip.com&gt; # drivers/irqchip/irq-atmel-aic-common.c
Acked-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt; # drivers/iio/adc/ti_am335x_adc.c
Acked-by: Uwe Kleine-König &lt;u.kleine-koenig@baylibre.com&gt; # drivers/pwm/pwm-samsung.c
Acked-by: Richard Leitner &lt;richard.leitner@linux.dev&gt; # drivers/usb/misc/usb251xb.c
Acked-by: Mark Brown &lt;broonie@kernel.org&gt; # sound/soc/codecs/arizona.c
Reviewed-by: Richard Fitzgerald &lt;rf@opensource.cirrus.com&gt; # sound/soc/codecs/arizona.c
Acked-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt; # arch/powerpc/sysdev/xive/spapr.c
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt; # clk
Signed-off-by: Luca Ceresoli &lt;luca.ceresoli@bootlin.com&gt;
Acked-by: Lee Jones &lt;lee@kernel.org&gt;
Link: https://lore.kernel.org/r/20240724-of_property_for_each_u32-v3-1-bea82ce429e2@bootlin.com
Signed-off-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/realtek: Add timer driver for rtl-otto platforms</title>
<updated>2024-07-12T14:07:06Z</updated>
<author>
<name>Chris Packham</name>
<email>chris.packham@alliedtelesis.co.nz</email>
</author>
<published>2024-07-10T04:35:21Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=4bdc3eaa102b6bedb0800f76f53eca516d5cf20c'/>
<id>urn:sha1:4bdc3eaa102b6bedb0800f76f53eca516d5cf20c</id>
<content type='text'>
The timer/counter block on the Realtek SoCs provides up to 5 timers. It
also includes a watchdog timer which is handled by the
realtek_otto_wdt.c driver.

One timer will be used per CPU as a local clock event generator. An
additional timer will be used as an overal stable clocksource.

Signed-off-by: Markus Stockhausen &lt;markus.stockhausen@gmx.de&gt;
Signed-off-by: Sander Vanheule &lt;sander@svanheule.net&gt;
Signed-off-by: Chris Packham &lt;chris.packham@alliedtelesis.co.nz&gt;
Link: https://lore.kernel.org/r/20240710043524.1535151-8-chris.packham@alliedtelesis.co.nz
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/mips-gic-timer: Correct sched_clock width</title>
<updated>2024-07-12T14:07:05Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-06-12T08:54:34Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=5e4bfd66eccaaab65b3d565cfe28483afeacaf1d'/>
<id>urn:sha1:5e4bfd66eccaaab65b3d565cfe28483afeacaf1d</id>
<content type='text'>
Counter width of GIC is configurable and can be read from a
register.

Use width value from the register for sched_clock.

Reviewed-by: Philippe Mathieu-Daudé &lt;philmd@linaro.org&gt;
Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Link: https://lore.kernel.org/r/20240612-mips-clks-v2-7-a57e6f49f3db@flygoat.com
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/mips-gic-timer: Refine rating computation</title>
<updated>2024-07-12T14:07:05Z</updated>
<author>
<name>Jiaxun Yang</name>
<email>jiaxun.yang@flygoat.com</email>
</author>
<published>2024-06-12T08:54:33Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=cc9b2c590ebacf656bb2063c2f6cbfb7ad7081f3'/>
<id>urn:sha1:cc9b2c590ebacf656bb2063c2f6cbfb7ad7081f3</id>
<content type='text'>
It is a good clocksource which usually go as fast as CPU core
and have a low access latency, so raise the base of rating
from Good to desired when we know that it has a stable frequency.

Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level clock, also cap rating
within current level.

Signed-off-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Link: https://lore.kernel.org/r/20240612-mips-clks-v2-6-a57e6f49f3db@flygoat.com
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/sh_cmt: Address race condition for clock events</title>
<updated>2024-07-12T14:07:05Z</updated>
<author>
<name>Niklas Söderlund</name>
<email>niklas.soderlund+renesas@ragnatech.se</email>
</author>
<published>2024-07-02T19:02:30Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=db19d3aa77612983a02bd223b3f273f896b243cf'/>
<id>urn:sha1:db19d3aa77612983a02bd223b3f273f896b243cf</id>
<content type='text'>
There is a race condition in the CMT interrupt handler. In the interrupt
handler the driver sets a driver private flag, FLAG_IRQCONTEXT. This
flag is used to indicate any call to set_next_event() should not be
directly propagated to the device, but instead cached. This is done as
the interrupt handler itself reprograms the device when needed before it
completes and this avoids this operation to take place twice.

It is unclear why this design was chosen, my suspicion is to allow the
struct clock_event_device.event_handler callback, which is called while
the FLAG_IRQCONTEXT is set, can update the next event without having to
write to the device twice.

Unfortunately there is a race between when the FLAG_IRQCONTEXT flag is
set and later cleared where the interrupt handler have already started to
write the next event to the device. If set_next_event() is called in
this window the value is only cached in the driver but not written. This
leads to the board to misbehave, or worse lockup and produce a splat.

   rcu: INFO: rcu_preempt detected stalls on CPUs/tasks:
   rcu:     0-...!: (0 ticks this GP) idle=f5e0/0/0x0 softirq=519/519 fqs=0 (false positive?)
   rcu:     (detected by 1, t=6502 jiffies, g=-595, q=77 ncpus=2)
   Sending NMI from CPU 1 to CPUs 0:
   NMI backtrace for cpu 0
   CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.10.0-rc5-arm64-renesas-00019-g74a6f86eaf1c-dirty #20
   Hardware name: Renesas Salvator-X 2nd version board based on r8a77965 (DT)
   pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
   pc : tick_check_broadcast_expired+0xc/0x40
   lr : cpu_idle_poll.isra.0+0x8c/0x168
   sp : ffff800081c63d70
   x29: ffff800081c63d70 x28: 00000000580000c8 x27: 00000000bfee5610
   x26: 0000000000000027 x25: 0000000000000000 x24: 0000000000000000
   x23: ffff00007fbb9100 x22: ffff8000818f1008 x21: ffff8000800ef07c
   x20: ffff800081c79ec0 x19: ffff800081c70c28 x18: 0000000000000000
   x17: 0000000000000000 x16: 0000000000000000 x15: 0000ffffc2c717d8
   x14: 0000000000000000 x13: ffff000009c18080 x12: ffff8000825f7fc0
   x11: 0000000000000000 x10: ffff8000818f3cd4 x9 : 0000000000000028
   x8 : ffff800081c79ec0 x7 : ffff800081c73000 x6 : 0000000000000000
   x5 : 0000000000000000 x4 : ffff7ffffe286000 x3 : 0000000000000000
   x2 : ffff7ffffe286000 x1 : ffff800082972900 x0 : ffff8000818f1008
   Call trace:
    tick_check_broadcast_expired+0xc/0x40
    do_idle+0x9c/0x280
    cpu_startup_entry+0x34/0x40
    kernel_init+0x0/0x11c
    do_one_initcall+0x0/0x260
    __primary_switched+0x80/0x88
   rcu: rcu_preempt kthread timer wakeup didn't happen for 6501 jiffies! g-595 f0x0 RCU_GP_WAIT_FQS(5) -&gt;state=0x402
   rcu:     Possible timer handling issue on cpu=0 timer-softirq=262
   rcu: rcu_preempt kthread starved for 6502 jiffies! g-595 f0x0 RCU_GP_WAIT_FQS(5) -&gt;state=0x402 -&gt;cpu=0
   rcu:     Unless rcu_preempt kthread gets sufficient CPU time, OOM is now expected behavior.
   rcu: RCU grace-period kthread stack dump:
   task:rcu_preempt     state:I stack:0     pid:15    tgid:15    ppid:2      flags:0x00000008
   Call trace:
    __switch_to+0xbc/0x100
    __schedule+0x358/0xbe0
    schedule+0x48/0x148
    schedule_timeout+0xc4/0x138
    rcu_gp_fqs_loop+0x12c/0x764
    rcu_gp_kthread+0x208/0x298
    kthread+0x10c/0x110
    ret_from_fork+0x10/0x20

The design have been part of the driver since it was first merged in
early 2009. It becomes increasingly harder to trigger the issue the
older kernel version one tries. It only takes a few boots on v6.10-rc5,
while hundreds of boots are needed to trigger it on v5.10.

Close the race condition by using the CMT channel lock for the two
competing sections. The channel lock was added to the driver after its
initial design.

Signed-off-by: Niklas Söderlund &lt;niklas.soderlund+renesas@ragnatech.se&gt;
Link: https://lore.kernel.org/r/20240702190230.3825292-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>clocksource/driver/arm_global_timer: Remove unnecessary ‘0’ values from err</title>
<updated>2024-07-12T14:07:05Z</updated>
<author>
<name>Li kunyu</name>
<email>kunyu@nfschina.com</email>
</author>
<published>2024-07-05T05:21:59Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=f3539a6a6998e1e662fdb30af435f239d5931c98'/>
<id>urn:sha1:f3539a6a6998e1e662fdb30af435f239d5931c98</id>
<content type='text'>
The 'err' variable is initialized whatever the code path, it is
pointless to initialize it when it is declared.

Signed-off-by: Li kunyu &lt;kunyu@nfschina.com&gt;
Link: https://lore.kernel.org/r/20240705052159.22235-1-kunyu@nfschina.com
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>clocksource/drivers/arm_arch_timer: Remove unnecessary ‘0’ values from irq</title>
<updated>2024-07-12T14:07:05Z</updated>
<author>
<name>Li kunyu</name>
<email>kunyu@nfschina.com</email>
</author>
<published>2024-07-05T04:07:29Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=7cbbcbd4b5bb68a6208b872612bb301683dc7114'/>
<id>urn:sha1:7cbbcbd4b5bb68a6208b872612bb301683dc7114</id>
<content type='text'>
The irq variable is initialized whatever the code path, it is poinless
to initialize when declaring it.

Signed-off-by: Li kunyu &lt;kunyu@nfschina.com&gt;
Link: https://lore.kernel.org/r/20240705040729.21961-1-kunyu@nfschina.com
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux</title>
<updated>2024-05-22T16:56:00Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-05-22T16:56:00Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=0bfbc914d9433d8ac2763a9ce99ce7721ee5c8e0'/>
<id>urn:sha1:0bfbc914d9433d8ac2763a9ce99ce7721ee5c8e0</id>
<content type='text'>
Pull RISC-V updates from Palmer Dabbelt:

 - Add byte/half-word compare-and-exchange, emulated via LR/SC loops

 - Support for Rust

 - Support for Zihintpause in hwprobe

 - Add PR_RISCV_SET_ICACHE_FLUSH_CTX prctl()

 - Support lockless lockrefs

* tag 'riscv-for-linus-6.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits)
  riscv: defconfig: Enable CONFIG_CLK_SOPHGO_CV1800
  riscv: select ARCH_HAS_FAST_MULTIPLIER
  riscv: mm: still create swiotlb buffer for kmalloc() bouncing if required
  riscv: Annotate pgtable_l{4,5}_enabled with __ro_after_init
  riscv: Remove redundant CONFIG_64BIT from pgtable_l{4,5}_enabled
  riscv: mm: Always use an ASID to flush mm contexts
  riscv: mm: Preserve global TLB entries when switching contexts
  riscv: mm: Make asid_bits a local variable
  riscv: mm: Use a fixed layout for the MM context ID
  riscv: mm: Introduce cntx2asid/cntx2version helper macros
  riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
  riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
  riscv: mm: Combine the SMP and UP TLB flush code
  riscv: Only send remote fences when some other CPU is online
  riscv: mm: Broadcast kernel TLB flushes only when needed
  riscv: Use IPIs for remote cache/TLB flushes by default
  riscv: Factor out page table TLB synchronization
  riscv: Flush the instruction cache during SMP bringup
  riscv: hwprobe: export Zihintpause ISA extension
  riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code
  ...
</content>
</entry>
<entry>
<title>clocksource/drivers/arm_arch_timer: Mark hisi_161010101_oem_info const</title>
<updated>2024-05-10T08:43:21Z</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2024-05-02T23:34:46Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=2030a7e11f161b4067bd4eadd984cdb36446fcca'/>
<id>urn:sha1:2030a7e11f161b4067bd4eadd984cdb36446fcca</id>
<content type='text'>
This isn't modified at runtime. Mark it const so it can move to
read-only data.

Cc: dann frazier &lt;dann.frazier@canonical.com&gt;
Cc: Hanjun Guo &lt;hanjun.guo@linaro.org&gt;
Cc: Marc Zyngier &lt;maz@kernel.org&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Reviewed-by: Hanjun Guo &lt;guohanjun@huawei.com&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/20240502233447.420888-1-swboyd@chromium.org
</content>
</entry>
<entry>
<title>clocksource/drivers/timer-ti-dm: Remove an unused field in struct dmtimer</title>
<updated>2024-05-10T08:41:52Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2024-04-30T21:42:39Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=e6f8bed209d5fa8602cda45930b0a331234d95ed'/>
<id>urn:sha1:e6f8bed209d5fa8602cda45930b0a331234d95ed</id>
<content type='text'>
In "struct dmtimer", the 'rate' field is unused.
Remove it.

Found with cppcheck, unusedStructMember.

Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Signed-off-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Link: https://lore.kernel.org/r/c9f7579922c587fce334a1aa9651f3189de7a00b.1714513336.git.christophe.jaillet@wanadoo.fr
</content>
</entry>
</feed>
