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<title>pm24.git/drivers/gpu/drm/amd/amdgpu, branch master</title>
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<updated>2024-12-06T21:16:41Z</updated>
<entry>
<title>Merge tag 'drm-fixes-2024-12-06' of https://gitlab.freedesktop.org/drm/kernel</title>
<updated>2024-12-06T21:16:41Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2024-12-06T21:16:41Z</published>
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<id>urn:sha1:c7cde621b2acfd6bc7d5f002b19b60ad2ed25df8</id>
<content type='text'>
Pull more drm fixes from Simona Vetter:
 "Due to mailing list unreliability we missed the amdgpu pull, hence
  part two with that now included:

   - amdgu: mostly display fixes + jpeg vcn 1.0, sriov, dcn4.0 resume
     fixes

   - amdkfd fixes"

* tag 'drm-fixes-2024-12-06' of https://gitlab.freedesktop.org/drm/kernel:
  drm/amdgpu: rework resume handling for display (v2)
  drm/amd/pm: fix and simplify workload handling
  Revert "drm/amd/pm: correct the workload setting"
  drm/amdgpu: fix sriov reinit late orders
  drm/amdgpu: Fix ISP hw init issue
  drm/amd/display: Add hblank borrowing support
  drm/amd/display: Limit VTotal range to max hw cap minus fp
  drm/amd/display: Correct prefetch calculation
  drm/amd/display: Add option to retrieve detile buffer size
  drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm
  drm/amdkfd: hard-code cacheline for gc943,gc944
  drm/amdkfd: add MEC version that supports no PCIe atomics for GFX12
  drm/amd/display: Fix programming backlight on OLED panels
  drm/amd: Sanity check the ACPI EDID
  drm/amdgpu/hdp7.0: do a posting read when flushing HDP
  drm/amdgpu/hdp6.0: do a posting read when flushing HDP
  drm/amdgpu/hdp5.2: do a posting read when flushing HDP
  drm/amdgpu/hdp5.0: do a posting read when flushing HDP
  drm/amdgpu/hdp4.0: do a posting read when flushing HDP
  drm/amdgpu/jpeg1.0: fix idle work handler
</content>
</entry>
<entry>
<title>drm/amdgpu: rework resume handling for display (v2)</title>
<updated>2024-12-03T23:19:23Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-25T18:59:09Z</published>
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<id>urn:sha1:73dae652dcac776296890da215ee7dec357a1032</id>
<content type='text'>
Split resume into a 3rd step to handle displays when DCC is
enabled on DCN 4.0.1.  Move display after the buffer funcs
have been re-enabled so that the GPU will do the move and
properly set the DCC metadata for DCN.

v2: fix fence irq resume ordering

Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.11.x
</content>
</entry>
<entry>
<title>drm/amdgpu: fix sriov reinit late orders</title>
<updated>2024-12-02T23:35:42Z</updated>
<author>
<name>Yiqing Yao</name>
<email>YiQing.Yao@amd.com</email>
</author>
<published>2024-11-26T10:36:11Z</published>
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<id>urn:sha1:f3bb57b66dc439dd129eb509a4965f1e1aeea2b8</id>
<content type='text'>
Use found block to call correct init/resume function on the block.
Set status.hw for resume and init.

Print re-init result again. Change to use dev_info.
Use amdgpu_device_ip_get_ip_block to get target block instead of
loop.

Fixes: 502d76308d45 ("drm/amdgpu: validate resume before function call")
Signed-off-by: Yiqing Yao &lt;YiQing.Yao@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Fix ISP hw init issue</title>
<updated>2024-12-02T23:35:36Z</updated>
<author>
<name>Pratap Nirujogi</name>
<email>pratap.nirujogi@amd.com</email>
</author>
<published>2024-11-29T19:52:08Z</published>
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<id>urn:sha1:274e3f4596446955bf17680fd4eb5489f5ecac00</id>
<content type='text'>
ISP hw_init is not called with the recent changes related
to hw init levels. AMDGPU_INIT_LEVEL_DEFAULT is ignoring
the ISP IP block as AMDGPU_IP_BLK_MASK_ALL is derived using
incorrect max number of IP blocks.

Update AMDGPU_IP_BLK_MASK_ALL to use AMDGPU_MAX_IP_NUM
instead of (AMDGPU_MAX_IP_NUM - 1) to fix the issue.

Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Fixes: 14f2fe34f5c6 ("drm/amdgpu: Add init levels")
Signed-off-by: Pratap Nirujogi &lt;pratap.nirujogi@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/hdp7.0: do a posting read when flushing HDP</title>
<updated>2024-12-02T23:05:04Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-28T08:05:24Z</published>
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<id>urn:sha1:689275140cb8e9f8ae59e545086fce51fb0b994a</id>
<content type='text'>
Need to read back to make sure the write goes through.

Cc: David Belanger &lt;david.belanger@amd.com&gt;
Reviewed-by: Frank Min &lt;frank.min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/hdp6.0: do a posting read when flushing HDP</title>
<updated>2024-12-02T22:38:47Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-22T16:24:38Z</published>
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<id>urn:sha1:abe1cbaec6cfe9fde609a15cd6a12c812282ce77</id>
<content type='text'>
Need to read back to make sure the write goes through.

Cc: David Belanger &lt;david.belanger@amd.com&gt;
Reviewed-by: Frank Min &lt;frank.min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/hdp5.2: do a posting read when flushing HDP</title>
<updated>2024-12-02T22:38:41Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-22T16:24:13Z</published>
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<id>urn:sha1:f756dbac1ce1d5f9a2b35e3b55fa429cf6336437</id>
<content type='text'>
Need to read back to make sure the write goes through.

Cc: David Belanger &lt;david.belanger@amd.com&gt;
Reviewed-by: Frank Min &lt;frank.min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/hdp5.0: do a posting read when flushing HDP</title>
<updated>2024-12-02T22:38:26Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-22T16:23:56Z</published>
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<id>urn:sha1:cf424020e040be35df05b682b546b255e74a420f</id>
<content type='text'>
Need to read back to make sure the write goes through.

Cc: David Belanger &lt;david.belanger@amd.com&gt;
Reviewed-by: Frank Min &lt;frank.min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/hdp4.0: do a posting read when flushing HDP</title>
<updated>2024-12-02T22:38:05Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-22T16:22:51Z</published>
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<id>urn:sha1:c9b8dcabb52afe88413ff135a0953e3cc4128483</id>
<content type='text'>
Need to read back to make sure the write goes through.

Cc: David Belanger &lt;david.belanger@amd.com&gt;
Reviewed-by: Frank Min &lt;frank.min@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu/jpeg1.0: fix idle work handler</title>
<updated>2024-12-02T22:37:31Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2024-11-22T19:00:05Z</published>
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<id>urn:sha1:c6c2f66372d5cba5ce85eed686901259333ed816</id>
<content type='text'>
On VCN 1.0, VCN and JPEG use the same worker thread so cancel
the vcn worker rather than jpeg.  On VCN 2.0 and newer
there are separate workers for each.

Fixes: 93df74873703 ("drm/amdgpu/jpeg: cancel the jpeg worker")
Tested-by: George Zhang &lt;george.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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