pm24.git/drivers/gpu/drm/amd/include/asic_reg, branch v4.5Unnamed repository; edit this file 'description' to name the repository.
https://git.kobert.dev/pm24.git/atom?h=v4.52015-12-21T21:42:12Zdrm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.h2015-12-21T21:42:12Zyanyang1young.yang@amd.com2015-08-17T06:15:20Zurn:sha1:3a287055aed6634d57d57da1977f1df3c9206945
Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by
new powerplay code for tonga and fiji.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
drm/amd: add new gfx8 register definitions for EDC2015-12-02T20:54:18ZAlex Deucheralexander.deucher@amd.com2015-11-24T22:42:02Zurn:sha1:aa5e24e5f8a83b19b1b19964f35562c7a42636e2
EDC is a RAS feature for on chip memory.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add GFX 8.1 register headers2015-10-28T20:49:03ZAlex Deucheralexander.deucher@amd.com2015-10-23T22:53:36Zurn:sha1:6bd53c4125e545a495fba63024d5522e33c600f5
Minor differences compared to GFX 8.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add Fiji smu 7.1.3 headers (v2)2015-08-17T20:50:25ZDavid Zhangdavid1.zhang@amd.com2015-07-08T11:13:25Zurn:sha1:d1c4dcfb76a0053ca7bcc90608b3699ac1e1b39d
v2: agd5f: prepare for release
Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
drm/amdgpu: add VCE 3.0 register headers2015-06-04T01:03:10ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:36:06Zurn:sha1:c481a6802e156a3666f1820674ed0c0828787bfa
These are register headers for the VCE (Video Codec Engine)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCE 2.0 register headers2015-06-04T01:03:09ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:35:39Zurn:sha1:683595a6f3c32d86952b57495bdecab370606b09
These are register headers for the VCE (Video Codec Engine)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add UVD 6.0 register headers2015-06-04T01:03:08ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:34:40Zurn:sha1:3b1e08cb29565d30d3bb87b26fefb126c1e00d89
These are register headers for the UVD (Universal Video Decoder)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add UVD 5.0 register headers2015-06-04T01:03:08ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:34:14Zurn:sha1:7aa27c37739c1bea219b744b351c3a74f6eb6674
These are register headers for the UVD (Universal Video Decoder)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add UVD 4.2 register headers2015-06-04T01:03:07ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:33:44Zurn:sha1:8630f839e0d0c439098b084d8867b82e3aa6084a
These are register headers for the UVD (Universal Video Decoder)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add SMU 8.0 register headers2015-06-04T01:03:06ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:32:09Zurn:sha1:47e6898750169db73219f77fbe467ddacd5aabda
These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>