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<title>pm24.git/drivers/gpu/drm/amd, branch rust-6.8</title>
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<id>https://git.kobert.dev/pm24.git/atom?h=rust-6.8</id>
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<updated>2023-12-06T21:05:32Z</updated>
<entry>
<title>drm/amdgpu: fix buffer funcs setting order on suspend</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-11-29T20:44:25Z</published>
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<id>urn:sha1:dab96d8b61aab1a4f99d0b86964a6c40e7bb1756</id>
<content type='text'>
We need to disable this after the last eviction
call, but before we disable the SDMA IP.

Fixes: b70438004a14 ("drm/amdgpu: move buffer funcs setting up a level")
Link: https://lore.kernel.org/r/87edgv4x3i.fsf@vps.thesusis.net
Reviewed-by: Luben Tuikov &lt;ltuikov89@gmail.com&gt;
Tested-by: Phillip Susi &lt;phill@thesusis.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Phillip Susi &lt;phill@thesusis.net&gt;
Cc: Luben Tuikov &lt;ltuikov89@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Avoid querying DRM MGCG status</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2023-11-30T11:05:58Z</published>
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<id>urn:sha1:27b024a88acba17c8e3a71ff4fd425064851e3b7</id>
<content type='text'>
MP0 v13.0.6 SOCs don't support DRM MGCG.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update HDP 4.4.2 clock gating flags</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2023-11-30T10:28:21Z</published>
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<id>urn:sha1:555e39f0270b1a1c51224044be9922b4c3a4c27f</id>
<content type='text'>
HDP 4.4.2 clockgating is enabled by default, update the flags
accordingly.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add NULL checks for function pointers</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2023-11-29T07:07:34Z</published>
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<id>urn:sha1:81577503efb49f4ad76af22f9941d72900ef4aab</id>
<content type='text'>
Check if function is implemented before making the call.

Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Restrict extended wait to PSP v13.0.6</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Lijo Lazar</name>
<email>lijo.lazar@amd.com</email>
</author>
<published>2023-11-29T12:36:55Z</published>
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<id>urn:sha1:6fce23a4d8c5f93bf80b7f122449fbb97f1e40dd</id>
<content type='text'>
Only PSPv13.0.6 SOCs take a longer time to reach steady state. Other
PSPv13 based SOCs don't need extended wait. Also, reduce PSPv13.0.6 wait
time.

Cc: stable@vger.kernel.org
Fixes: fc5988907156 ("drm/amdgpu: update retry times for psp vmbx wait")
Fixes: d8c1925ba8cd ("drm/amdgpu: update retry times for psp BL wait")
Link: https://lore.kernel.org/amd-gfx/34dd4c66-f7bf-44aa-af8f-c82889dd652c@amd.com/
Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Asad Kamal &lt;asad.kamal@amd.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-11-30T22:34:07Z</published>
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<id>urn:sha1:5b750b22530fe53bf7fd6a30baacd53ada26911b</id>
<content type='text'>
Does the same thing as:
commit 6740ec97bcdb ("drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml2")

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202311302107.hUDXVyWT-lkp@intel.com/
Fixes: 67e38874b85b ("drm/amd/display: Increase num voltage states to 40")
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Cc: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Cc: Samson Tam &lt;samson.tam@amd.com&gt;
Cc: Harry Wentland &lt;harry.wentland@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: optimize the printing order of error data</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Yang Wang</name>
<email>kevinyang.wang@amd.com</email>
</author>
<published>2023-12-04T02:44:32Z</published>
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<id>urn:sha1:dbf3850d12baf3ba8a80c302f538d1b01940aef7</id>
<content type='text'>
sort error data list to optimize the printing order.

Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Update fw version for boot time error query</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-11-20T02:43:02Z</published>
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<id>urn:sha1:0e8af20517197934cc04f8e361c6bbe198c327fd</id>
<content type='text'>
Boot time error query is not available until fw a10109

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Stanley Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: support new mca smu error code decoding</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Yang Wang</name>
<email>kevinyang.wang@amd.com</email>
</author>
<published>2023-12-04T02:17:57Z</published>
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<id>urn:sha1:37c57631c18661c4c0dc415e75afd143ed89e098</id>
<content type='text'>
support new mca smu error code decoding from smu 85.86.0 for smu v13.0.6

Signed-off-by: Yang Wang &lt;kevinyang.wang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/swsmu: update smu v14_0_0 driver if version and metrics table</title>
<updated>2023-12-06T21:05:32Z</updated>
<author>
<name>Li Ma</name>
<email>li.ma@amd.com</email>
</author>
<published>2023-11-14T08:17:51Z</published>
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<id>urn:sha1:78825df90d427b26964bf9610eaac30542ee9e2d</id>
<content type='text'>
Increment the driver if version and add new mems to the mertics table.

Signed-off-by: Li Ma &lt;li.ma@amd.com&gt;
Reviewed-by: Yifan Zhang &lt;yifan1.zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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