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<title>pm24.git/drivers/gpu/drm, branch v6.3-rc7</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>https://git.kobert.dev/pm24.git/atom/drivers/gpu/drm?h=v6.3-rc7</id>
<link rel='self' href='https://git.kobert.dev/pm24.git/atom/drivers/gpu/drm?h=v6.3-rc7'/>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/'/>
<updated>2023-04-13T18:47:58Z</updated>
<entry>
<title>Merge tag 'drm-misc-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes</title>
<updated>2023-04-13T18:47:58Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2023-04-13T18:47:58Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=cab2932213c5cd72a9e04e5e82002e81b946592b'/>
<id>urn:sha1:cab2932213c5cd72a9e04e5e82002e81b946592b</id>
<content type='text'>
Short summary of fixes pull:

 * armada: Fix double free
 * fb: Clear FB_ACTIVATE_KD_TEXT in ioctl
 * nouveau: Add missing callbacks
 * scheduler: Fix use-after-free error

Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
From: Thomas Zimmermann &lt;tzimmermann@suse.de&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230413184233.GA8148@linux-uq9g
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-fixes-2023-04-13' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes</title>
<updated>2023-04-13T12:24:45Z</updated>
<author>
<name>Daniel Vetter</name>
<email>daniel.vetter@ffwll.ch</email>
</author>
<published>2023-04-13T12:24:44Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=a552b73f36cb3e59fd2015307fde8ff53874d1af'/>
<id>urn:sha1:a552b73f36cb3e59fd2015307fde8ff53874d1af</id>
<content type='text'>
drm/i915 fixes for v6.3-rc7:
- Fix dual link DSI for TGL+

Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
From: Jani Nikula &lt;jani.nikula@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/877cugckzu.fsf@intel.com
</content>
</entry>
<entry>
<title>drm/amd/pm: correct the pcie link state check for SMU13</title>
<updated>2023-04-12T20:11:22Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2023-04-07T09:12:15Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=b9a24d8bd51e2db425602fa82d7f4c06aa3db852'/>
<id>urn:sha1:b9a24d8bd51e2db425602fa82d7f4c06aa3db852</id>
<content type='text'>
Update the driver implementations to fit those data exposed
by PMFW.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
</entry>
<entry>
<title>drm/amd/pm: correct SMU13.0.7 max shader clock reporting</title>
<updated>2023-04-12T20:11:21Z</updated>
<author>
<name>Horatio Zhang</name>
<email>Hongkun.Zhang@amd.com</email>
</author>
<published>2023-04-06T05:32:14Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=85e0689eb6b10cd3b2fb455d1b3f4d4d0b13ff78'/>
<id>urn:sha1:85e0689eb6b10cd3b2fb455d1b3f4d4d0b13ff78</id>
<content type='text'>
Correct the max shader clock reporting on SMU
13.0.7.

Signed-off-by: Horatio Zhang &lt;Hongkun.Zhang@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
</entry>
<entry>
<title>drm/amd/pm: correct SMU13.0.7 pstate profiling clock settings</title>
<updated>2023-04-12T20:11:21Z</updated>
<author>
<name>Horatio Zhang</name>
<email>Hongkun.Zhang@amd.com</email>
</author>
<published>2023-04-06T03:17:38Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=f06b8887e3ef4f50098d3a949aef392c529c831a'/>
<id>urn:sha1:f06b8887e3ef4f50098d3a949aef392c529c831a</id>
<content type='text'>
Correct the pstate standard/peak profiling mode clock
settings for SMU13.0.7.

Signed-off-by: Horatio Zhang &lt;Hongkun.Zhang@amd.com&gt;
Reviewed-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
</entry>
<entry>
<title>drm/amd/display: Pass the right info to drm_dp_remove_payload</title>
<updated>2023-04-12T20:11:17Z</updated>
<author>
<name>Wayne Lin</name>
<email>Wayne.Lin@amd.com</email>
</author>
<published>2023-02-17T05:26:56Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=b8ca445f550a9a079134f836466ddda3bfad6108'/>
<id>urn:sha1:b8ca445f550a9a079134f836466ddda3bfad6108</id>
<content type='text'>
[Why &amp; How]
drm_dp_remove_payload() interface was changed. Correct amdgpu dm code
to pass the right parameter to the drm helper function.

Reviewed-by: Jerry Zuo &lt;Jerry.Zuo@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixes</title>
<updated>2023-04-12T10:01:32Z</updated>
<author>
<name>Maarten Lankhorst</name>
<email>maarten.lankhorst@linux.intel.com</email>
</author>
<published>2023-04-12T10:01:32Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=5603effb8295ada8419408d038a34ca89d658229'/>
<id>urn:sha1:5603effb8295ada8419408d038a34ca89d658229</id>
<content type='text'>
We were stuck on rc2, should at least attempt to track drm-fixes
slightly.

Signed-off-by: Maarten Lankhorst &lt;maarten.lankhorst@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/armada: Fix a potential double free in an error handling path</title>
<updated>2023-04-11T18:29:33Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2021-12-26T16:34:16Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=b89ce1177d42d5c124e83f3858818cd4e6a2c46f'/>
<id>urn:sha1:b89ce1177d42d5c124e83f3858818cd4e6a2c46f</id>
<content type='text'>
'priv' is a managed resource, so there is no need to free it explicitly or
there will be a double free().

Fixes: 90ad200b4cbc ("drm/armada: Use devm_drm_dev_alloc")
Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/c4f3c9207a9fce35cb6dd2cc60e755275961588a.1640536364.git.christophe.jaillet@wanadoo.fr
</content>
</entry>
<entry>
<title>drm/nouveau/fb: add missing sysmen flush callbacks</title>
<updated>2023-04-11T10:35:46Z</updated>
<author>
<name>Karol Herbst</name>
<email>kherbst@redhat.com</email>
</author>
<published>2023-04-05T11:04:55Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=86d8740dae5a397d8344ae75f8758103c1fcba97'/>
<id>urn:sha1:86d8740dae5a397d8344ae75f8758103c1fcba97</id>
<content type='text'>
Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/203
Fixes: 5728d064190e1 ("drm/nouveau/fb: handle sysmem flush page from common code")
Signed-off-by: Karol Herbst &lt;kherbst@redhat.com&gt;
Reviewed-by: Lyude Paul &lt;lyude@redhat.com&gt;
Reviewed-by: Ben Skeggs &lt;bskeggs@redhat.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230405110455.1368428-1-kherbst@redhat.com
</content>
</entry>
<entry>
<title>drm/i915/dsi: fix DSS CTL register offsets for TGL+</title>
<updated>2023-04-11T08:41:57Z</updated>
<author>
<name>Jani Nikula</name>
<email>jani.nikula@intel.com</email>
</author>
<published>2023-03-01T15:14:09Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=6b8446859c971a5783a2cdc90adf32e64de3bd23'/>
<id>urn:sha1:6b8446859c971a5783a2cdc90adf32e64de3bd23</id>
<content type='text'>
On TGL+ the DSS control registers are at different offsets, and there's
one per pipe. Fix the offsets to fix dual link DSI for TGL+.

There would be helpers for this in the DSC code, but just do the quick
fix now for DSI. Long term, we should probably move all the DSS handling
into intel_vdsc.c, so exporting the helpers seems counter-productive.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232
Cc: Ville Syrjala &lt;ville.syrjala@linux.intel.com&gt;
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
Reviewed-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20230301151409.1581574-1-jani.nikula@intel.com
(cherry picked from commit 1a62dd9895dca78bee28bba3a36f08836fdd143d)
</content>
</entry>
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