Unnamed repository; edit this file 'description' to name the repository. https://git.kobert.dev/pm24.git/atom/drivers/gpu?h=v4.5-rc7 2016-03-04T21:53:25Z 2016-03-04T21:53:25Z Dave Airlie airlied@redhat.com 2016-03-04T21:53:25Z urn:sha1:26bae5e04c3570728787f809b13546a8169fdf95 drm/tegra: Fixes for v4.5-rc7 Two small fixes that restore PRIME support. * tag 'drm/tegra/for-4.5-rc7' of git://anongit.freedesktop.org/tegra/linux: gpu: host1x: Set DMA ops on device creation gpu: host1x: Set DMA mask 2016-03-04T15:24:57Z Alexandre Courbot acourbot@nvidia.com 2016-02-26T09:06:53Z urn:sha1:c95469aa5a188384ccf8ac520ece931c66caf8aa Currently host1x-instanciated devices have their dma_ops left to NULL, which makes any DMA operation (like buffer import) on ARM64 fallback to the dummy_dma_ops and fail with an error. This patch calls of_dma_configure() with the host1x node when creating such a device, so the proper DMA operations are set. Suggested-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2016-03-04T15:24:56Z Alexandre Courbot acourbot@nvidia.com 2016-02-26T09:06:52Z urn:sha1:097452e61366a939a4772332181cea7cdcc74760 The default DMA mask covers a 32 bits address range, but host1x devices can address a larger range on TK1 and TX1. Set the DMA mask to the range addressable when we use the IOMMU to prevent the use of bounce buffers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2016-03-04T03:51:53Z Dave Airlie airlied@redhat.com 2016-03-04T03:51:53Z urn:sha1:0dff9738ec6dddf701821a6aa477ced809f17ef0 Small conflict as I had the balance in my tree already for testing. * tag 'drm-intel-fixes-2016-03-03' of git://anongit.freedesktop.org/drm-intel: drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM) drm/i915/skl: Fix power domain suspend sequence 2016-03-03T01:37:07Z Dave Airlie airlied@redhat.com 2016-03-03T01:37:07Z urn:sha1:f0511e66114a6414cfca92d7b94118913a0c11ff Fixes for radeon and amdgpu: - Fix GPUVM flushing on CI and VI - Misc DPM and Powerplay fixes - VCE DPM fixes for CZ/ST - DP hotplug fix * 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: return from atombios_dp_get_dpcd only when error drm/amdgpu/cz: remove commented out call to enable vce pg drm/amdgpu/powerplay/cz: enable/disable vce dpm independent of vce pg drm/amdgpu/cz: enable/disable vce dpm even if vce pg is disabled drm/amdgpu/gfx8: specify which engine to wait before vm flush drm/amdgpu: apply gfx_v8 fixes to gfx_v7 as well drm/amd/powerplay: send event to notify powerplay all modules are initialized. drm/amd/powerplay: export AMD_PP_EVENT_COMPLETE_INIT task to amdgpu. drm/radeon/pm: update current crtc info after setting the powerstate drm/amdgpu/pm: update current crtc info after setting the powerstate 2016-03-02T16:01:25Z Arindam Nath arindam.nath@amd.com 2016-03-02T11:49:01Z urn:sha1:0b39c531cfa12dad54eac238c2e303b994df1ef7 In amdgpu_connector_hotplug(), we need to start DP link training only after we have received DPCD. The function amdgpu_atombios_dp_get_dpcd() returns non-zero value only when an error condition is met, otherwise returns zero. So in case the function encounters an error, we need to skip rest of the code and return from amdgpu_connector_hotplug() immediately. Only when we are successfull in reading DPCD pin, we should carry on with turning-on the monitor. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 2016-03-02T16:01:24Z Alex Deucher alexander.deucher@amd.com 2016-02-29T21:11:07Z urn:sha1:89913ea615754163ae9a066c9c1b95aa2a2f51b4 This code path is not currently enabled now that we properly respect the vce pg flags, so uncomment the actual pg calls so the code is as it should be we are eventually able to enable vce pg. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2016-03-02T16:01:24Z Alex Deucher alexander.deucher@amd.com 2016-02-29T20:29:48Z urn:sha1:370afa7ac5dc6c65cebeaee841ae700eb2387a55 If we don't disable it when vce is not in use, we use extra power if vce pg is disabled. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2016-03-02T16:01:23Z Alex Deucher alexander.deucher@amd.com 2016-02-25T16:24:52Z urn:sha1:b3dae7828399ef316e3fabf7e82c6415cb03a02e I missed this when cleaning up the vce pg handling. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2016-03-02T16:01:23Z Chunming Zhou David1.Zhou@amd.com 2016-02-29T06:12:38Z urn:sha1:9cac537332f5502c103415b25609548c276a09f8 Select between me and pfp properly. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>