pm24.git/drivers/irqchip/Makefile, branch master

irqchip: Add T-HEAD C900 ACLINT SSWI driver

2024-11-06T23:28:27Z

Add a driver for the T-HEAD C900 ACLINT SSWI device. This device allows the system with T-HEAD cpus to send ipi via fast device interface. Signed-off-by: Inochi Amaoto Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241031060859.722258-3-inochiama@gmail.com

irqchip/aspeed-intc: Add AST27XX INTC support

2024-10-17T19:35:28Z

Support Aspeed Interrupt Controller on Aspeed Silicon SoCs. ASPEED interrupt controller(INTC) maps the internal interrupt sources to a parent interrupt controller, which can be GIC or INTC. Signed-off-by: Kevin Chen Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241016022410.1154574-3-kevin_chen@aspeedtech.com

irqchip: Add RZ/V2H(P) Interrupt Control Unit (ICU) driver

2024-10-15T22:01:06Z

Add driver for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU). This driver supports the external interrupts NMI, IRQn, and TINTn. Signed-off-by: Fabrizio Castro Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20241009230817.798582-3-fabrizio.castro.jz@renesas.com

irqchip/loongarch-avec: Add AVEC irqchip support

2024-08-23T18:40:27Z

Introduce the advanced extended interrupt controllers (AVECINTC). This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. The whole topology of irqchips in LoongArch machines looks like this if AVECINTC is supported: +-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+ Co-developed-by: Jianmin Lv Signed-off-by: Jianmin Lv Co-developed-by: Liupu Wang Signed-off-by: Liupu Wang Co-developed-by: Huacai Chen Signed-off-by: Huacai Chen Signed-off-by: Tianyang Zhang Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20240823104337.25577-2-zhangtianyang@loongson.cn

Merge tag 'irq-msi-2024-07-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2024-07-22T21:02:19Z

Pull MSI interrupt updates from Thomas Gleixner: "Switch ARM/ARM64 over to the modern per device MSI domains. This simplifies the handling of platform MSI and wire to MSI controllers and removes about 500 lines of legacy code. Aside of that it paves the way for ARM/ARM64 to utilize the dynamic allocation of PCI/MSI interrupts and to support the upcoming non standard IMS (Interrupt Message Store) mechanism on PCIe devices" * tag 'irq-msi-2024-07-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip/gic-v3-its: Correctly fish out the DID for platform MSI irqchip/gic-v3-its: Correctly honor the RID remapping genirq/msi: Move msi_device_data to core genirq/msi: Remove platform MSI leftovers irqchip/irq-mvebu-icu: Remove platform MSI leftovers irqchip/irq-mvebu-sei: Switch to MSI parent irqchip/mvebu-odmi: Switch to parent MSI irqchip/mvebu-gicp: Switch to MSI parent irqchip/irq-mvebu-icu: Prepare for real per device MSI irqchip/imx-mu-msi: Switch to MSI parent irqchip/gic-v2m: Switch to device MSI irqchip/gic_v3_mbi: Switch over to parent domain genirq/msi: Remove platform_msi_create_device_domain() irqchip/mbigen: Remove platform_msi_create_device_domain() fallback irqchip/gic-v3-its: Switch platform MSI to MSI parent irqchip/irq-msi-lib: Prepare for DOMAIN_BUS_WIRED_TO_MSI irqchip/mbigen: Prepare for real per device MSI irqchip/irq-msi-lib: Prepare for DEVICE MSI to replace platform MSI irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X] irqchip/irq-msi-lib: Prepare for PCI MSI/MSIX ...

irqchip/gic-v3-its: Switch platform MSI to MSI parent

2024-07-18T18:31:20Z

Similar to the previous conversion of the PCI/MSI support lift the prepare() callback from the existing platform MSI code and enable platform MSI and the related device domain bus tokens in select and the child domain initialization code. All platform MSI users are automatically using the new per device MSI model now. Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142235.271734124@linutronix.de

irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X]

2024-07-18T18:31:20Z

The its_pci_msi_prepare() function from the ITS-PCI/MSI code provides the 'global' PCI/MSI domains. Move this function to the ITS-MSI parent code and amend the function to use the domain hardware size, which is the MSI[X] vector count, for allocating the ITS slots for the PCI device. Enable PCI matching in msi_parent_ops and provide the necessary update to the ITS specific child domain initialization function so that the prepare callback gets invoked on allocations. The latter might be optimized to do the allocation right at the point where the child domain is initialized, but keep it simple for now. Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142235.024567623@linutronix.de

irqchip/gic-v3-its: Provide MSI parent infrastructure

2024-07-18T18:31:19Z

To support per device MSI domains the ITS must provide MSI parent domain functionality. Provide the basic skeleton for this: - msi_parent_ops - child domain init callback - the MSI parent flag set in irqdomain::flags This does not make ITS a functional parent domain as there is no bit set in the bus_select_mask yet, but it provides the base to implement PCI and platform MSI support gradually on top. Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142234.903076277@linutronix.de

irqchip: Provide irq-msi-lib

2024-07-18T18:31:19Z

All irqdomains which provide MSI parent domain functionality for per device MSI domains need to provide a select() callback for the irqdomain and a function to initialize the child domain. Most of these functions would just be copy&paste with minimal modifications, so provide a library function which implements the required functionality and is customizable via parent_domain::msi_parent_ops. The check for the supported bus tokens in msi_lib_init_dev_msi_info() is expanded step by step within the next patches. Signed-off-by: Thomas Gleixner Signed-off-by: Anna-Maria Behnsen Signed-off-by: Shivamurthy Shastri Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20240623142234.840975799@linutronix.de

Revert "Loongarch: Support loongarch avec"

2024-06-25T05:40:08Z

This reverts commit 760d7e719499d64beea62bfcf53938fb233bb6e7. This results in build failures and has other issues according to Tianyang. Reported-by: kernel test robot Signed-off-by: Thomas Gleixner Cc: Tianyang Zhang Closes: https://lore.kernel.org/oe-kbuild-all/202406240451.ygBFNyJ3-lkp@intel.com/