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<title>pm24.git/drivers/irqchip, branch v4.0</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<id>https://git.kobert.dev/pm24.git/atom?h=v4.0</id>
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<updated>2015-03-29T19:34:05Z</updated>
<entry>
<title>Merge branch 'irqchip/urgent-gic' into irqchip/urgent</title>
<updated>2015-03-29T19:34:05Z</updated>
<author>
<name>Jason Cooper</name>
<email>jason@lakedaemon.net</email>
</author>
<published>2015-03-29T19:34:05Z</published>
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<id>urn:sha1:dbcf988653e91681305189fc8b8c54aa4ae9033c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Use non-cacheable accesses when no shareability</title>
<updated>2015-03-29T19:25:57Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2015-03-27T14:15:05Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=241a386c7dbb8b0db400a1f92f2ebe3b10eb661d'/>
<id>urn:sha1:241a386c7dbb8b0db400a1f92f2ebe3b10eb661d</id>
<content type='text'>
If the ITS or the redistributors report their shareability as zero,
then it is important to make sure they will no generate any cacheable
traffic, as this is unlikely to produce the expected result.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1427465705-17126-5-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Fix PROP/PEND and BASE/CBASE confusion</title>
<updated>2015-03-29T19:25:51Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2015-03-27T14:15:04Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=4ad3e3634a6cbe916722c7113c5b488d52c7a3dc'/>
<id>urn:sha1:4ad3e3634a6cbe916722c7113c5b488d52c7a3dc</id>
<content type='text'>
The ITS driver sometime mixes up the use of GICR_PROPBASE bitfields
for the GICR_PENDBASE register, and GITS_BASER for GICR_CBASE.

This does not lead to any observable bug because similar bits are
at the same location, but this just make the code even harder to
understand...

This patch provides the required #defines and fixes the mixup.

Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1427465705-17126-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Fix device ID encoding</title>
<updated>2015-03-29T19:25:49Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2015-03-27T14:15:03Z</published>
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<id>urn:sha1:7e195ba03738dec72fe337dcd3cb3c3c2bd66c30</id>
<content type='text'>
When building ITS commands which have the device ID in it, we
should mask off the whole upper 32 bits of the first command word
before inserting the new value in there.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1427465705-17126-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Fix encoding of collection's target redistributor</title>
<updated>2015-03-29T19:25:45Z</updated>
<author>
<name>Marc Zyngier</name>
<email>marc.zyngier@arm.com</email>
</author>
<published>2015-03-27T14:15:02Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=263fcd312deffb9bf10f007f958dccfa64a807f5'/>
<id>urn:sha1:263fcd312deffb9bf10f007f958dccfa64a807f5</id>
<content type='text'>
With a monolithic GICv3, redistributors are addressed using a linear
number, while a distributed implementation uses physical addresses.

When encoding a target address into a command, we strip the lower
16 bits, as redistributors are always 64kB aligned. This works
perfectly well with a distributed implementation, but has the
silly effect of always encoding target 0 in the monolithic case
(unless you have more than 64k CPUs, of course).

The obvious fix is to shift the linear target number by 16 when
computing the target address, so that we don't loose any precious
bit.

Reported-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1427465705-17126-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>Merge branch 'irqchip/urgent-gic' into irqchip/urgent</title>
<updated>2015-03-15T01:41:26Z</updated>
<author>
<name>Jason Cooper</name>
<email>jason@lakedaemon.net</email>
</author>
<published>2015-03-15T01:41:26Z</published>
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<id>urn:sha1:aaa95f74563a1c5a42db5fec43415b9a92ea7f7b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Support safe initialization</title>
<updated>2015-03-08T05:34:58Z</updated>
<author>
<name>Yun Wu</name>
<email>wuyun.wu@huawei.com</email>
</author>
<published>2015-03-06T16:37:50Z</published>
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<id>urn:sha1:4559fbb3a9b1bde46afc739fa6c300826acdc19c</id>
<content type='text'>
It's unsafe to change the configurations of an activated ITS directly
since this will lead to unpredictable results. This patch guarantees
the ITSes being initialized are quiescent.

Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Yun Wu &lt;wuyun.wu@huawei.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1425659870-11832-12-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Define macros for GITS_CTLR fields</title>
<updated>2015-03-08T05:34:35Z</updated>
<author>
<name>Yun Wu</name>
<email>wuyun.wu@huawei.com</email>
</author>
<published>2015-03-06T16:37:49Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=7cb991164a46992a499ecdc77b17f8ac94bdb75f'/>
<id>urn:sha1:7cb991164a46992a499ecdc77b17f8ac94bdb75f</id>
<content type='text'>
Define macros for GITS_CTLR fields to avoid using magic numbers.

Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Yun Wu &lt;wuyun.wu@huawei.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1425659870-11832-11-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Add limitation to page order</title>
<updated>2015-03-08T05:34:21Z</updated>
<author>
<name>Yun Wu</name>
<email>wuyun.wu@huawei.com</email>
</author>
<published>2015-03-06T16:37:48Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=1d27704a26313b9ed7463d4bfc6eda29e2bb3180'/>
<id>urn:sha1:1d27704a26313b9ed7463d4bfc6eda29e2bb3180</id>
<content type='text'>
When required size of Device Table is out of the page allocator's
capability, the whole ITS will fail in probing. This actually is
not the hardware's problem and is mainly a limitation of the kernel
page allocator. This patch will keep ITS going on to the next
initializaion stage with an explicit warning.

Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Signed-off-by: Yun Wu &lt;wuyun.wu@huawei.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1425659870-11832-10-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>irqchip: gicv3-its: Use 64KB page as default granule</title>
<updated>2015-03-08T05:34:12Z</updated>
<author>
<name>Yun Wu</name>
<email>wuyun.wu@huawei.com</email>
</author>
<published>2015-03-06T16:37:47Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=790b57aed156d22d6c7101a37adc78a621be1167'/>
<id>urn:sha1:790b57aed156d22d6c7101a37adc78a621be1167</id>
<content type='text'>
The field of page size in register GITS_BASERn might be read-only
if an implementation only supports a single, fixed page size. But
currently the ITS driver will throw out an error when PAGE_SIZE
is less than the minimum size supported by an ITS. So addressing
this problem by using 64KB pages as default granule for all the
ITS base tables.

Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
[maz: fixed bug breaking non Device Table allocations]
Signed-off-by: Yun Wu &lt;wuyun.wu@huawei.com&gt;
Signed-off-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
Link: https://lkml.kernel.org/r/1425659870-11832-9-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
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