pm24.git/drivers/mailbox, branch v5.4-rc6

mailbox: qcom-apcs: fix max_register value

2019-09-17T05:54:29Z

The mailbox length is 0x1000 hence the max_register value is 0xFFC. Fixes: c6a8b171ca8e ("mailbox: qcom: Convert APCS IPC driver to use regmap") Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Jassi Brar

mailbox: qcom: Add support for IPQ8074 APCS

2019-09-17T05:53:35Z

Add support of IPQ8074 with IPC register offset as 8. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Jassi Brar

mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs

2019-09-17T05:46:24Z

Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs. Reviewed-by: Bjorn Andersson Signed-off-by: Sibi Sankar Signed-off-by: Jassi Brar

mbox: qcom: replace integer with valid macro

2019-09-17T05:46:05Z

Use the correct macro when registering the platform device. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Jassi Brar

mbox: qcom: add APCS child device for QCS404

2019-09-17T05:46:00Z

There is clock controller functionality in the APCS hardware block of qcs404 devices similar to msm8916. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Jassi Brar

mailbox: mediatek: cmdq: clear the event in cmdq initial flow

2019-09-17T05:40:05Z

GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu Reviewed-by: Matthias Brugger Signed-off-by: Jassi Brar

mailbox: mediatek: cmdq: support mt8183 gce function

2019-09-17T05:40:05Z

add mt8183 compatible name for supporting gce function Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu Signed-off-by: Jassi Brar

mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data

2019-09-17T05:40:05Z

The interrupt mask and thread number has positive correlation, so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate it by thread number. Signed-off-by: Bibby Hsieh Reviewed-by: CK Hu Reviewed-by: Matthias Brugger Signed-off-by: Jassi Brar

mailbox: armada-37xx-rwtm: Use device-managed registration API

2019-09-17T05:38:43Z

Use devm_mbox_controller_register to get rid of redundant remove function. Signed-off-by: Chuhong Yuan Signed-off-by: Jassi Brar

Merge tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration

2019-07-14T23:36:51Z

Pull mailbox updates from Jassi Brar: - stm32: race fix by adding a spinlock - mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling * tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle failed named mailbox channel request mailbox: tegra: avoid resume NULL mailboxes mailbox: tegra: hsp: add noirq resume mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly mailbox: imx: Clear GIEn bit at shutdown mailbox: omap: Add support for TI K3 SoCs dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox: arm_mhu: reorder header inclusion and drop unneeded ones mailbox: stm32_ipcc: add spinlock to fix channels concurrent access