pm24.git/drivers/mmc/host, branch master

mmc: sdhci-pci: Add DMI quirk for missing CD GPIO on Vexia Edu Atla 10 tablet

2024-12-02T14:06:03Z

The Vexia Edu Atla 10 tablet distributed to schools in the Spanish Andalucía region has no ACPI fwnode associated with the SDHCI controller for its microsd-slot and thus has no ACPI GPIO resource info. This causes the following error to be logged and the slot to not work: [ 10.572113] sdhci-pci 0000:00:12.0: failed to setup card detect gpio Add a DMI quirk table for providing gpiod_lookup_tables with manually provided CD GPIO info and use this DMI table to provide the CD GPIO info on this tablet. This fixes the microsd-slot not working. Signed-off-by: Hans de Goede Acked-by: Adrian Hunter Cc: stable@vger.kernel.org Message-ID: <20241118210049.311079-1-hdegoede@redhat.com> Signed-off-by: Ulf Hansson

mmc: Merge branch fixes into next

2024-11-12T18:41:24Z

Merge the mmc fixes for v6.12-rc[n] into the next branch, to allow them to get tested together with the new mmc changes that are targeted for v6.13. Signed-off-by: Ulf Hansson

Revert "mmc: dw_mmc: Fix IDMAC operation with pages bigger than 4K"

2024-11-12T18:40:40Z

The commit 8396c793ffdf ("mmc: dw_mmc: Fix IDMAC operation with pages bigger than 4K") increased the max_req_size, even for 4K pages, causing various issues: - Panic booting the kernel/rootfs from an SD card on Rockchip RK3566 - Panic booting the kernel/rootfs from an SD card on StarFive JH7100 - "swiotlb buffer is full" and data corruption on StarFive JH7110 At this stage no fix have been found, so it's probably better to just revert the change. This reverts commit 8396c793ffdf28bb8aee7cfe0891080f8cab7890. Cc: stable@vger.kernel.org Cc: Sam Protsenko Fixes: 8396c793ffdf ("mmc: dw_mmc: Fix IDMAC operation with pages bigger than 4K") Closes: https://lore.kernel.org/linux-mmc/614692b4-1dbe-31b8-a34d-cb6db1909bb7@w6rz.net/ Closes: https://lore.kernel.org/linux-mmc/CAC8uq=Ppnmv98mpa1CrWLawWoPnu5abtU69v-=G-P7ysATQ2Pw@mail.gmail.com/ Signed-off-by: Aurelien Jarno Message-ID: <20241110114700.622372-1-aurelien@aurel32.net> Signed-off-by: Ulf Hansson

mmc: mtk-sd: Fix MMC_CAP2_CRYPTO flag setting

2024-11-12T18:36:30Z

Currently, the MMC_CAP2_CRYPTO flag is set by default for eMMC hosts. However, this flag should not be set for hosts that do not support inline encryption. The 'crypto' clock, as described in the documentation, is used for data encryption and decryption. Therefore, only hosts that are configured with this 'crypto' clock should have the MMC_CAP2_CRYPTO flag set. Fixes: 7b438d0377fb ("mmc: mtk-sd: add Inline Crypto Engine clock control") Fixes: ed299eda8fbb ("mmc: mtk-sd: fix devm_clk_get_optional usage") Signed-off-by: Andy-ld Lu Cc: stable@vger.kernel.org Message-ID: <20241111085039.26527-1-andy-ld.lu@mediatek.com> Signed-off-by: Ulf Hansson

mmc: mtk-sd: Fix error handle of probe function

2024-11-12T17:31:05Z

In the probe function, it goes to 'release_mem' label and returns after some procedure failure. But if the clocks (partial or all) have been enabled previously, they would not be disabled in msdc_runtime_suspend, since runtime PM is not yet enabled for this case. That cause mmc related clocks always on during system suspend and block suspend flow. Below log is from a SDCard issue of MT8196 chromebook, it returns -ETIMEOUT while polling clock stable in the msdc_ungate_clock() and probe failed, but the enabled clocks could not be disabled anyway. [ 129.059253] clk_chk_dev_pm_suspend() [ 129.350119] suspend warning: msdcpll is on [ 129.354494] [ck_msdc30_1_sel : enabled, 1, 1, 191999939, ck_msdcpll_d2] [ 129.362787] [ck_msdcpll_d2 : enabled, 1, 1, 191999939, msdcpll] [ 129.371041] [ck_msdc30_1_ck : enabled, 1, 1, 191999939, ck_msdc30_1_sel] [ 129.379295] [msdcpll : enabled, 1, 1, 383999878, clk26m] Add a new 'release_clk' label and reorder the error handle functions to make sure the clocks be disabled after probe failure. Fixes: ffaea6ebfe9c ("mmc: mtk-sd: Use readl_poll_timeout instead of open-coded polling") Fixes: 7a2fa8eed936 ("mmc: mtk-sd: use devm_mmc_alloc_host") Signed-off-by: Andy-ld Lu Reviewed-by: AngeloGioacchino Del Regno Cc: stable@vger.kernel.org Message-ID: <20241107121215.5201-1-andy-ld.lu@mediatek.com> Signed-off-by: Ulf Hansson

mmc: sunxi-mmc: Fix A100 compatible description

2024-11-12T17:22:57Z

It turns out that the Allwinner A100/A133 SoC only supports 8K DMA blocks (13 bits wide), for both the SD/SDIO and eMMC instances. And while this alone would make a trivial fix, the H616 falls back to the A100 compatible string, so we have to now match the H616 compatible string explicitly against the description advertising 64K DMA blocks. As the A100 is now compatible with the D1 description, let the A100 compatible string point to that block instead, and introduce an explicit match against the H616 string, pointing to the old description. Also remove the redundant setting of clk_delays to NULL on the way. Fixes: 3536b82e5853 ("mmc: sunxi: add support for A100 mmc controller") Cc: stable@vger.kernel.org Signed-off-by: Andre Przywara Tested-by: Parthiban Nallathambi Reviewed-by: Chen-Yu Tsai Message-ID: <20241107014240.24669-1-andre.przywara@arm.com> Signed-off-by: Ulf Hansson

mmc: sdhci-esdhc-imx: Update esdhc sysctl dtocv bitmask

2024-11-04T11:16:39Z

NXP ESDHC supports setting data timeout using uSDHCx_SYS_CTRL register DTOCV bits (bits 16-19). Currently the driver accesses those bits by 32-bit write using SDHCI_TIMEOUT_CONTROL (0x2E) defined in drivers/mmc/host/sdhci.h. This is offset by two bytes relative to uSDHCx_SYS_CTRL (0x2C). The driver also defines ESDHC_SYS_CTRL_DTOCV_MASK as first 4 bits, which is correct relative to SDHCI_TIMEOUT_CONTROL but not relative to uSDHCx_SYS_CTRL. The definition carrying control register in its name is therefore inconsistent. Update the bitmask definition for bits 16-19 to be correct relative to control register base. Update the esdhc_set_timeout function to set timeout value at control register base, not timeout offset. This solves a purely cosmetic problem. Signed-off-by: Josua Mayer Reviewed-by: Haibo Chen Acked-by: Adrian Hunter Message-ID: <20241101-imx-emmc-reset-v3-2-184965eed476@solid-run.com> Signed-off-by: Ulf Hansson

mmc: sdhci-esdhc-imx: Implement emmc hardware reset

2024-11-04T11:16:30Z

NXP ESDHC supports control of native emmc reset signal when pinmux is set accordingly, using uSDHCx_SYS_CTRL register IPP_RST_N bit. Documentation is available in NXP i.MX6Q Reference Manual. Implement the hw_reset function in sdhci_ops asserting reset for at least 1us and waiting at least 200us after deassertion. Lower bounds are based on: JEDEC Standard No. 84-B51, 6.15.10 H/W Reset Operation, page 159. Upper bounds are chosen allowing flexibility to the scheduler. Tested on SolidRun i.MX8DXL SoM with a scope, and confirmed that eMMC is still accessible after boot: - eMMC extcsd has RST_N_FUNCTION=0x01 - sdhc node has cap-mmc-hw-reset - pinmux set for EMMC0_RESET_B - Linux v5.15 Signed-off-by: Josua Mayer Reviewed-by: Haibo Chen Acked-by: Adrian Hunter Message-ID: <20241101-imx-emmc-reset-v3-1-184965eed476@solid-run.com> Signed-off-by: Ulf Hansson

mmc: sdhci-uhs2: correction a warning caused by incorrect type in argument

2024-11-04T11:11:17Z

There is a type issue in the argument in the uhs2_dev_cmd() that will generate a warning when building the kernel. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202410260525.ZUuPhMJz-lkp@intel.com/ Suggested-by: Adrian Hunter Signed-off-by: Ben Chuang Signed-off-by: Victor Shih Message-ID: <20241101104416.4954-1-victorshihgli@gmail.com> Signed-off-by: Ulf Hansson

mmc: sdhci-uhs2: Remove unnecessary variables

2024-10-31T16:36:34Z

There are unnecessary variables in the sdhci_uhs2_send_command() that will generate a warning when building the kernel. Let's drop them! Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202410252107.y9EgrTbA-lkp@intel.com/ Signed-off-by: Ben Chuang Signed-off-by: Victor Shih Acked-by: Adrian Hunter Message-ID: <20241030112216.4057-2-victorshihgli@gmail.com> Signed-off-by: Ulf Hansson