pm24.git/drivers/phy/rockchip, branch cpufreq-rust

Merge tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2025-01-29T22:32:38Z

Pull phy updates from Vinod Koul: "Lots of Qualcomm and Rockchip device support. New Support: - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY - Rockchip rk3576 combo phy support Updates: - Drop Shengyang for JH7110 maintainer - Freescale hdmi register calculation optimization - Rockchip pcie phy mutex and regmap updates" * tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits) dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY phy: rockchip: phy-rockchip-typec: Fix Copyright description dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs phy: qcom-qusb2: Add support for QCS615 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings phy: core: Simplify API of_phy_simple_xlate() implementation phy: sun4i-usb: Remove unused of_gpio.h phy: HiSilicon: Don't use "proxy" headers phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle() phy: qualcomm: qmp-pcie: add support for SAR2130P phy: qualcomm: qmp-pcie: define several new registers phy: qualcomm: qmp-pcie: split PCS_LANE1 region phy: qualcomm: qmp-combo: add support for SAR2130P dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found phy: freescale: fsl-samsung-hdmi: Expand Integer divider range phy: rockchip-naneng-combo: add rk3576 support dt-bindings: phy: rockchip: add rk3576 compatible ...

phy: rockchip: phy-rockchip-typec: Fix Copyright description

2024-12-24T19:47:33Z

The company name has update to Rockchip Electronics Co., Ltd. since 2021. And change Co.Ltd to Co., Ltd. to fix mail server warning: DBL_SPAM(6.50)[co.ltd:url]; Signed-off-by: Andy Yan Reviewed-by: Kever Yang Acked-by: Heiko Stuebner Link: https://lore.kernel.org/r/20241216100739.3726293-1-andyshrk@163.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Set drvdata before enabling runtime PM

2024-12-08T16:12:07Z

In some cases, rk_hdptx_phy_runtime_resume() may be invoked before platform_set_drvdata() is executed in ->probe(), leading to a NULL pointer dereference when using the return of dev_get_drvdata(). Ensure platform_set_drvdata() is called before devm_pm_runtime_enable(). Reported-by: Dmitry Osipenko Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20241023-phy-sam-hdptx-rpm-fix-v1-1-87f4c994e346@collabora.com Signed-off-by: Vinod Koul

phy: rockchip-naneng-combo: add rk3576 support

2024-12-08T15:49:49Z

Rockchip RK3576 integrates two naneng-combo PHY, PHY0 is used for PCIE and SATA, PHY1 is used for PCIE, SATA and USB3. This adds device specific data support. Signed-off-by: Kever Yang Signed-off-by: William Wu Signed-off-by: Frank Wang Reviewed-by: Heiko Stuebner Test-by: Kever Yang Link: https://lore.kernel.org/r/20241106021357.19782-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul

phy: rockchip: naneng-combphy: fix phy reset

2024-12-04T14:19:08Z

Currently, the USB port via combophy on the RK3528/RK3588 SoC is broken. usb usb8-port1: Cannot enable. Maybe the USB cable is bad? This is due to the combphy of RK3528/RK3588 SoC has multiple resets, but only "phy resets" need assert and deassert, "apb resets" don't need. So change the driver to only match the phy resets, which is also what the vendor kernel does. Fixes: 7160820d742a ("phy: rockchip: add naneng combo phy for RK3568") Cc: FUKAUMI Naoki Cc: Michael Zimmermann Signed-off-by: Chukun Pan Reviewed-by: Heiko Stuebner Tested-by: FUKAUMI Naoki Link: https://lore.kernel.org/r/20241122073006.99309-2-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul

phy: rockchip-pcie: Use guard notation when acquiring mutex

2024-12-04T13:27:08Z

Using guard notation makes the code more compact and error handling more robust by ensuring that mutexes are released in all code paths when control leaves critical section. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20241012071919.3726-7-linux.amoon@gmail.com Signed-off-by: Vinod Koul

phy: rockchip-pcie: Refactor mutex handling in rockchip_pcie_phy_power_on()

2024-12-04T13:27:08Z

Refactor the mutex handling in the rockchip_pcie_phy_power_on() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_deassert() or regmap_read_poll_timeout() function, with 0 indicating success and an error code indicating failure. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20241012071919.3726-6-linux.amoon@gmail.com Signed-off-by: Vinod Koul

phy: rockchip-pcie: Refactor mutex handling in rockchip_pcie_phy_power_off()

2024-12-04T13:27:08Z

Refactor the mutex handling in the rockchip_pcie_phy_power_off() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_assert() function, with 0 indicating success and an error code indicating failure Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20241012071919.3726-5-linux.amoon@gmail.com Signed-off-by: Vinod Koul

phy: rockchip-pcie: Use regmap_read_poll_timeout() for PCIe reference clk PLL status

2024-12-04T13:27:08Z

Replace open-coded phy PCIe reference clk PLL status polling with regmap_read_poll_timeout API. This change simplifies the code without altering functionality. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20241012071919.3726-4-linux.amoon@gmail.com Signed-off-by: Vinod Koul

phy: rockchip-pcie: Use devm_clk_get_enabled() helper

2024-12-04T13:27:07Z

Use devm_clk_get_enabled() instead of devm_clk_get() to make the code cleaner and avoid calling clk_disable_unprepare(), as this is exactly what this function does. Use the dev_err_probe() helper to simplify error handling during probe. Refactor the mutex handling in the rockchip_pcie_phy_init() function to improve code readability and maintainability. The goto statement has been removed, and the mutex_unlock call is now directly within the conditional block. Return the result of reset_control_assert() function, with 0 indicating success and an error code indicating failure Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20241012071919.3726-3-linux.amoon@gmail.com Signed-off-by: Vinod Koul