pm24.git/drivers/pinctrl/intel, branch v4.18

Merge tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-06-07T20:56:45Z

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for v4.18. No core changes this time! Just a calm all-over-the-place drivers, updates and fixes cycle as it seems. New drivers/subdrivers: - Actions Semiconductor S900 driver with more Actions variants for S700, S500 in the pipe. Also generic GPIO support on top of the same driver and IRQ support is in the pipe. - Renesas r8a77470 PFC support. - Renesas r8a77990 PFC support. - Allwinner Sunxi H6 R_PIO support. - Rockchip PX30 support. - Meson Meson8m2 support. - Remove support for the ill-fated Samsung Exynos 5440 SoC. Improvements: - Context save/restore support in pinctrl-single. - External interrupt support for the Mediatek MT7622. - Qualcomm ACPI HID QCOM8002 supported. Fixes: - Fix up suspend/resume support for Exynos 5433. - Fix Strago DMI fixes on the Intel Cherryview" * tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: cherryview: limit Strago DMI workarounds to version 1.0 pinctrl: at91-pio4: add missing of_node_put pinctrl: armada-37xx: Fix spurious irq management gpiolib: discourage gpiochip_add_pin[group]_range for DT pinctrls pinctrl: msm: fix gpio-hog related boot issues MAINTAINERS: update entry for Mediatek pin controller pinctrl: mediatek: remove unused fields in struct mtk_eint_hw pinctrl: mediatek: use generic EINT register maps for each SoC pinctrl: mediatek: add EINT support to MT7622 SoC pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit dt-bindings: pinctrl: add external interrupt support to MT7622 pinctrl pinctrl: freescale: Switch to SPDX identifier pinctrl: samsung: Fix suspend/resume for Exynos5433 GPF1..5 banks pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin comments pinctrl: sh-pfc: r8a77965: Add I2C pin support pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functions pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions pinctrl: sh-pfc: r8a77990: Add bias pinconf support pinctrl: sh-pfc: Initial R8A77990 PFC support ...

pinctrl: cherryview: limit Strago DMI workarounds to version 1.0

2018-06-04T06:34:14Z

As Google/Intel will fix the BIOS/Coreboot issues with hardcoding virtual interrupt numbers for keyboard/touchpad/touchscreen controllers in ACPI tables, they will also update BOARD version number from 1.0 to 1.1. Let's limit the DMI quirks that try to preserve virtual IRQ numbers on Strago boards to those that still carry older BIOSes. Note that ideally not BOARD but BIOS version should have been updated. However the BIOS version used by Chrome devices has format of Google_BUILD.BRANCH.PATCH which is not well suited for DMI matching as we do not have "less than" match mode for DMI data. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=197953 Signed-off-by: Dmitry Torokhov Acked-by: Mika Westerberg Reviewed-by: Guenter Roeck Acked-by: Andy Shevchenko Signed-off-by: Linus Walleij

pinctrl: sunrisepoint: Align GPIO number space with Windows

2018-05-02T12:36:00Z

It turns out that the Windows GPIO driver for Sunrisepoint PCH-H uses similar bank structure than it does for Cannon Lake with the exception that here the bank size is always 24 pins. Starting from pad group E the BIOS/Windows GPIO numbering does not match the hardware anymore but instead there are gaps to make each pad group ("bank") consume exactly 24 pins. Because of this Linux does not use correct pins for GpioIo/GpioIo resources exposed by the BIOS. This patch aligns the GPIO number space with BIOS/Windows to make sure the same numbering scheme is used in Linux as well following what we did already for Intel Cannon Lake. Link: https://bugzilla.redhat.com/show_bug.cgi?id=1543769 Reported-by: Vivien FRASCA Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij

pinctrl: cherryview: Associate IRQ descriptors to irqdomain

2018-05-02T12:35:59Z

When we dropped the custom Linux GPIO translation it resulted that the IRQ numbers changed slightly as well. Normally this would be fine because everyone is expected to use controller relative GPIO numbers and ACPI GpioIo/GpioInt resources. However, there is a certain set of Intel_Strago based Chromebooks where i8042 keyboard controller IRQ number is hardcoded be 182 (this is corrected with newer coreboot but the older ones still have the hardcoded Linux IRQ number). Because of this hardcoded IRQ number keyboard on those systems accidentally broke again. Fix this by iteratively associating IRQ descriptors to the chip irqdomain so that there are no gaps on those systems. Other systems are not affected. Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") Link: https://bugzilla.kernel.org/show_bug.cgi?id=199463 Reported-by: Sultan Alsawaf Signed-off-by: Mika Westerberg Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij

pinctrl: intel: Implement intel_gpio_get_direction callback

2018-03-23T03:07:22Z

Allows querying GPIO direction from the pad config register. If the pad is not in GPIO mode, return an error. Signed-off-by: Javier Arteaga Reviewed-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2018-02-02T22:22:53Z

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.16 kernel cycle. Like with GPIO it is actually a bit calm this time. Core changes: - After lengthy discussions and partly due to my ignorance, we have merged a patch making pinctrl_force_default() and pinctrl_force_sleep() reprogram the states into the hardware of any hogged pins, even if they are already in the desired state. This only apply to hogged pins since groups of pins owned by drivers need to be managed by each driver, lest they could not do things like runtime PM and put pins to sleeping state even if the system as a whole is not in sleep. New drivers: - New driver for the Microsemi Ocelot SoC. This is used in ethernet switches. - The X-Powers AXP209 GPIO driver was extended to also deal with pin control and moved over from the GPIO subsystem. This circuit is a mixed-mode integrated circuit which is part of AllWinner designs. - New subdriver for the Qualcomm MSM8998 SoC, core of a high end mobile devices (phones) chipset. - New subdriver for the ST Microelectronics STM32MP157 MPU and STM32F769 MCU from the STM32 family. - New subdriver for the MediaTek MT7622 SoC. This is used for routers, repeater, gateways and such network infrastructure. - New subdriver for the NXP (former Freescale) i.MX 6ULL. This SoC has multimedia features and target "smart devices", I guess in-car entertainment, in-flight entertainment, industrial control panels etc. General improvements: - Incremental improvements on the SH-PFC subdrivers for things like the CAN bus. - Enable the glitch filter on Baytrail GPIOs used for interrupts. - Proper handling of pins to GPIO ranges on the Semtec SX150X - An IRQ setup ordering fix on MCP23S08. - A good set of janitorial coding style fixes" * tag 'pinctrl-v4.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (102 commits) pinctrl: mcp23s08: fix irq setup order pinctrl: Forward declare struct device pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding pinctrl: stm32: add STM32F769 MCU support pinctrl: sx150x: Add a static gpio/pinctrl pin range mapping pinctrl: sx150x: Register pinctrl before adding the gpiochip pinctrl: sx150x: Unregister the pinctrl on release pinctrl: ingenic: Remove redundant dev_err call in ingenic_pinctrl_probe() pinctrl: sprd: Use seq_putc() in sprd_pinconf_group_dbg_show() pinctrl: pinmux: Use seq_putc() in pinmux_pins_show() pinctrl: abx500: Use seq_putc() in abx500_gpio_dbg_show() pinctrl: mediatek: mt7622: align error handling of mtk_hw_get_value call pinctrl: mediatek: mt7622: fix potential uninitialized value being returned pinctrl: uniphier: refactor drive strength get/set functions pinctrl: imx7ulp: constify struct imx_cfg_params_decode pinctrl: imx: constify struct imx_pinctrl_soc_info pinctrl: imx7d: simplify imx7d_pinctrl_probe pinctrl: imx: use struct imx_pinctrl_soc_info as a const pinctrl: sunxi-pinctrl: fix pin funtion can not be match correctly. pinctrl: qcom: Add msm8998 pinctrl driver ...

pinctrl: baytrail: Enable glitch filter for GPIOs used as interrupts

2018-01-08T07:15:46Z

On some systems, some PCB traces attached to GpioInts are routed in such a way that they pick up enough interference to constantly (many times per second) trigger. Enabling glitch-filtering fixes this. Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: cherryview: Mask all interrupts on Intel_Strago based systems

2017-12-12T08:51:38Z

Guenter Roeck reported an interrupt storm on a prototype system which is based on Cyan Chromebook. The root cause turned out to be a incorrectly configured pin that triggers spurious interrupts. This will be fixed in coreboot but currently we need to prevent the interrupt storm from happening by masking all interrupts (but not GPEs) on those systems. Link: https://bugzilla.kernel.org/show_bug.cgi?id=197953 Fixes: bcb48cca23ec ("pinctrl: cherryview: Do not mask all interrupts in probe") Reported-and-tested-by: Guenter Roeck Reported-by: Dmitry Torokhov Signed-off-by: Mika Westerberg Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij

pinctrl: intel: ensure error return ret is initialized

2017-12-07T08:59:39Z

In the (unlikely) event that community->ngpps is zero, or if every gpp->gpio_base is less than zero, then an ininitialized value in ret is returned by function intel_gpio_add_pin_ranges. Fix this by ensuring ret is initialized to zero. It's a moot point, but I think it is worthwhile ensuring this corner case is fixed. Detected by CoverityScan, CID#1462415 ("Uninitialized scalar variable") Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Signed-off-by: Colin Ian King Acked-by: Mika Westerberg Signed-off-by: Linus Walleij

pinctrl: intel: Initialize GPIO properly when used through irqchip

2017-12-02T12:11:04Z

When a GPIO is requested using gpiod_get_* APIs the intel pinctrl driver switches the pin to GPIO mode and makes sure interrupts are routed to the GPIO hardware instead of IOAPIC. However, if the GPIO is used directly through irqchip, as is the case with many I2C-HID devices where I2C core automatically configures interrupt for the device, the pin is not initialized as GPIO. Instead we rely that the BIOS configures the pin accordingly which seems not to be the case at least in Asus X540NA SKU3 with Focaltech touchpad. When the pin is not properly configured it might result weird behaviour like interrupts suddenly stop firing completely and the touchpad stops responding to user input. Fix this by properly initializing the pin to GPIO mode also when it is used directly through irqchip. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Reported-by: Daniel Drake Reported-and-tested-by: Chris Chiu Signed-off-by: Mika Westerberg Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij