staging: add missing SPDX lines to Makefile files

2019-04-03T09:10:15Z

There are a few remaining drivers/staging/*/Makefile files that do not have SPDX identifiers in them. Add the correct GPL-2.0 identifier to them to make scanning tools happy. Reviewed-by: Mukesh Ojha Signed-off-by: Greg Kroah-Hartman

staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core

2018-07-24T12:14:13Z

This IP core has read and write AXI-Stream FIFOs, the contents of which can be accessed from the AXI4 memory-mapped interface. This is useful for transferring data from a processor into the FPGA fabric. The driver creates a character device that can be read/written to with standard open/read/write/close. See Xilinx PG080 document for IP details. https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf The driver currently supports only store-forward mode with a 32-bit AXI4 Lite interface. DOES NOT support: - cut-through mode - AXI4 (non-lite) Signed-off-by: Jacob Feder Signed-off-by: Greg Kroah-Hartman

pm24.git/drivers/staging/axis-fifo/Makefile, branch master

staging: add missing SPDX lines to Makefile files

staging: add driver for Xilinx AXI-Stream FIFO v4.1 IP core