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<title>pm24.git/tools/testing/selftests/kvm/include/riscv, branch cpufreq-rust</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<id>https://git.kobert.dev/pm24.git/atom?h=cpufreq-rust</id>
<link rel='self' href='https://git.kobert.dev/pm24.git/atom?h=cpufreq-rust'/>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/'/>
<updated>2024-04-26T07:44:10Z</updated>
<entry>
<title>KVM: riscv: selftests: Add a test for PMU snapshot functionality</title>
<updated>2024-04-26T07:44:10Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:38Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=13cb706e28d9d4d3259954eb08c57b990e4429ea'/>
<id>urn:sha1:13cb706e28d9d4d3259954eb08c57b990e4429ea</id>
<content type='text'>
Verify PMU snapshot functionality by setting up the shared memory
correctly and reading the counter values from the shared memory
instead of the CSR.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-23-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add SBI PMU extension definitions</title>
<updated>2024-04-26T07:44:04Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:36Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=3203b9474356503ac5a28030b5d46d85a6491c5f'/>
<id>urn:sha1:3203b9474356503ac5a28030b5d46d85a6491c5f</id>
<content type='text'>
The SBI PMU extension definition is required for upcoming SBI PMU
selftests.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-21-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add helper functions for extension checks</title>
<updated>2024-04-26T07:44:00Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:34Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=97be675bfdb5086a6ad1aeeaa43df78b1afd5a0d'/>
<id>urn:sha1:97be675bfdb5086a6ad1aeeaa43df78b1afd5a0d</id>
<content type='text'>
__vcpu_has_ext can check both SBI and ISA extensions when the first
argument is properly converted to SBI/ISA extension IDs. Introduce
two helper functions to make life easier for developers so they
don't have to worry about the conversions.

Replace the current usages as well with new helpers.

Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-19-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Move sbi definitions to its own header file</title>
<updated>2024-04-26T07:43:57Z</updated>
<author>
<name>Atish Patra</name>
<email>atishp@rivosinc.com</email>
</author>
<published>2024-04-20T15:17:33Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=9408a23fac62d31de067bd2b0099eb9151395345'/>
<id>urn:sha1:9408a23fac62d31de067bd2b0099eb9151395345</id>
<content type='text'>
The SBI definitions will continue to grow. Move the sbi related
definitions to its own header file from processor.h

Suggested-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
Link: https://lore.kernel.org/r/20240420151741.962500-18-atishp@rivosinc.com
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'kvm-x86-selftests-6.9' of https://github.com/kvm-x86/linux into HEAD</title>
<updated>2024-03-11T14:20:35Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2024-03-11T14:20:35Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=4d4c02852abf01059e45a188f16f13f7ec78371c'/>
<id>urn:sha1:4d4c02852abf01059e45a188f16f13f7ec78371c</id>
<content type='text'>
KVM selftests changes for 6.9:

 - Add macros to reduce the amount of boilerplate code needed to write "simple"
   selftests, and to utilize selftest TAP infrastructure, which is especially
   beneficial for KVM selftests with multiple testcases.

 - Add basic smoke tests for SEV and SEV-ES, along with a pile of library
   support for handling private/encrypted/protected memory.

 - Fix benign bugs where tests neglect to close() guest_memfd files.
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add sstc timer test</title>
<updated>2024-03-06T15:23:29Z</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:42Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d'/>
<id>urn:sha1:d0b94bcbb04262b9ffe6e172223e8cbb663a2c9d</id>
<content type='text'>
Add a KVM selftests to validate the Sstc timer functionality.
The test was ported from arm64 arch timer test.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Change vcpu_has_ext to a common function</title>
<updated>2024-03-06T15:23:27Z</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:41Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=812806bd1e70f79cc69061f9fd9bb1d367990d37'/>
<id>urn:sha1:812806bd1e70f79cc69061f9fd9bb1d367990d37</id>
<content type='text'>
Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext
so that other test cases can use it for vCPU extension check.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Add exception handling support</title>
<updated>2024-03-06T15:21:41Z</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:39Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=38f680c25ece49c1f8ff55ee78dca0ee4e1793a6'/>
<id>urn:sha1:38f680c25ece49c1f8ff55ee78dca0ee4e1793a6</id>
<content type='text'>
Add the infrastructure for guest exception handling in riscv selftests.
Customized handlers can be enabled by vm_install_exception_handler(vector)
or vm_install_interrupt_handler().

The code is inspired from that of x86/arm64.

Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>KVM: selftests: Allow tagging protected memory in guest page tables</title>
<updated>2024-02-29T00:39:49Z</updated>
<author>
<name>Peter Gonda</name>
<email>pgonda@google.com</email>
</author>
<published>2024-02-23T00:42:54Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=be1bd4c5394ff7eb6f14aaf8005824ed1946bb82'/>
<id>urn:sha1:be1bd4c5394ff7eb6f14aaf8005824ed1946bb82</id>
<content type='text'>
Add support for tagging and untagging guest physical address, e.g. to
allow x86's SEV and TDX guests to embed shared vs. private information in
the GPA.  SEV (encryption, a.k.a. C-bit) and TDX (shared, a.k.a. S-bit)
steal bits from the guest's physical address space that is consumed by the
CPU metadata, i.e. effectively aliases the "real" GPA.

Implement generic "tagging" so that the shared vs. private metadata can be
managed by x86 without bleeding too many details into common code.

Cc: Paolo Bonzini &lt;pbonzini@redhat.com&gt;
Cc: Sean Christopherson &lt;seanjc@google.com&gt;
Cc: Vishal Annapurve &lt;vannapurve@google.com&gt;
Cc: Ackerly Tng &lt;ackerleytng@google.com&gt;
cc: Andrew Jones &lt;andrew.jones@linux.dev&gt;
Cc: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Cc: Michael Roth &lt;michael.roth@amd.com&gt;
Tested-by: Carlos Bilbao &lt;carlos.bilbao@amd.com&gt;
Originally-by: Michael Roth &lt;michael.roth@amd.com&gt;
Signed-off-by: Peter Gonda &lt;pgonda@google.com&gt;
Link: https://lore.kernel.org/r/20240223004258.3104051-8-seanjc@google.com
Signed-off-by: Sean Christopherson &lt;seanjc@google.com&gt;
</content>
</entry>
<entry>
<title>KVM: riscv: selftests: Switch to use macro from csr.h</title>
<updated>2024-02-26T04:44:07Z</updated>
<author>
<name>Haibo Xu</name>
<email>haibo1.xu@intel.com</email>
</author>
<published>2024-01-22T09:58:38Z</published>
<link rel='alternate' type='text/html' href='https://git.kobert.dev/pm24.git/commit/?id=feb2c8fae3b8703408f01a8db822dd05b1a576ee'/>
<id>urn:sha1:feb2c8fae3b8703408f01a8db822dd05b1a576ee</id>
<content type='text'>
Signed-off-by: Haibo Xu &lt;haibo1.xu@intel.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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