diff options
| author | Likun Gao <Likun.Gao@amd.com> | 2023-06-28 15:37:37 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-02 16:18:10 -0400 |
| commit | 6628f7762b8e23e7524d61c7ed126662348fd6b4 (patch) | |
| tree | f3950e2441c349fc3981966ffa74ce369dc6b948 | |
| parent | 785f0f9fe74202e64a7af94a8efc92d4bed742b0 (diff) | |
drm/amdgpu: set mes fw address for mes v12
Split the function of mes fimrware address setting
from mes firmware load for mes v12, as it's also
needed for rlc autoload.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 37 |
1 files changed, 28 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 1bf12fc1f72e..a9bf06ad0202 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -596,13 +596,36 @@ static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable) } } +static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev) +{ + uint64_t ucode_addr; + int pipe; + + mes_v12_0_enable(adev, false); + + mutex_lock(&adev->srbm_mutex); + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + /* me=3, queue=0 */ + soc21_grbm_select(adev, 3, pipe, 0, 0); + + /* set ucode start address */ + ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; + WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, + lower_32_bits(ucode_addr)); + WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, + upper_32_bits(ucode_addr)); + + soc21_grbm_select(adev, 0, 0, 0, 0); + } + mutex_unlock(&adev->srbm_mutex); +} + /* This function is for backdoor MES firmware */ static int mes_v12_0_load_microcode(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe, bool prime_icache) { int r; uint32_t data; - uint64_t ucode_addr; mes_v12_0_enable(adev, false); @@ -625,13 +648,6 @@ static int mes_v12_0_load_microcode(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); - /* set ucode start address */ - ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; - WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, - lower_32_bits(ucode_addr)); - WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, - upper_32_bits(ucode_addr)); - /* set ucode fimrware address */ WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); @@ -1158,7 +1174,10 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) return r; } - } + mes_v12_0_set_ucode_start_addr(adev); + + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) + mes_v12_0_set_ucode_start_addr(adev); mes_v12_0_enable(adev, true); |