Merge tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
 "This tme we have again a big pile of qcom-qmp-* changes, one new
  driver and bunch of new hardware support.

  New hardware support:

   - Allwinner H616 USB PHY and A100 DPHY support

   - TI J721s2, J784s4 and J721e support

   - Freescale i.MX8MP PCIe PHY support

   - New driver for Renesas Ethernet SERDES supporting R-Car S4-8

   - Qualcomm SM8450 PCIe1 PHY support in EP mode

   - Qualcomm SC8280XP PCIe PHY support (including x4 mode)

   - Fixed Qualcomm SC8280XP USB4-USB3-DP PHY DT bindings

  Updates:

   - A big pile of updates on qcom-qmp-* drivers following the driver
     split and reorganization merged earlier

   - Phy order of API calls documentation update"

* tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (174 commits)
  phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module support
  dt-bindings: phy-j721e-wiz: add j721s2 compatible string
  phy: use devm_platform_get_and_ioremap_resource()
  phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant
  phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
  phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last
  phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional
  dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
  dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property
  phy: qcom-qmp-pcie: drop redundant clock allocation
  phy: qcom-qmp-usb: drop redundant clock allocation
  phy: qcom-qmp: drop unused type header
  phy: qcom-qmp-usb: drop sc8280xp reference-clock source
  dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: drop reference-clock source
  phy: qcom-qmp-combo: add support for updated sc8280xp binding
  phy: qcom-qmp-combo: rename DP_PHY register pointer
  phy: qcom-qmp-combo: rename common-register pointers
  phy: qcom-qmp-combo: clean up DP clock callbacks
  phy: qcom-qmp-combo: separate clock and provider registration
  phy: qcom-qmp-combo: add clock registration helper
  ...

1 files changed, 42 insertions, 6 deletions

diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index da7cac537e15..3a6d686383cf 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -54,6 +54,7 @@ properties:
       - ti,dm814-phy-gmii-sel
       - ti,am654-phy-gmii-sel
       - ti,j7200-cpsw5g-phy-gmii-sel
+      - ti,j721e-cpsw9g-phy-gmii-sel
 
   reg:
     maxItems: 1
@@ -63,14 +64,17 @@ properties:
   ti,qsgmii-main-ports:
     $ref: /schemas/types.yaml#/definitions/uint32-array
     description: |
-      Required only for QSGMII mode. Array to select the port for
-      QSGMII main mode. Rest of the ports are selected as QSGMII_SUB
-      ports automatically. Any one of the 4 CPSW5G ports can act as the
-      main port with the rest of them being the QSGMII_SUB ports.
-    maxItems: 1
+      Required only for QSGMII mode. Array to select the port/s for QSGMII
+      main mode. The size of the array corresponds to the number of QSGMII
+      interfaces and thus, the number of distinct QSGMII main ports,
+      supported by the device. If the device supports two QSGMII interfaces
+      but only one QSGMII interface is desired, repeat the QSGMII main port
+      value corresponding to the QSGMII interface in the array.
+    minItems: 1
+    maxItems: 2
     items:
       minimum: 1
-      maximum: 4
+      maximum: 8
 
 allOf:
   - if:
@@ -81,6 +85,8 @@ allOf:
               - ti,dra7xx-phy-gmii-sel
               - ti,dm814-phy-gmii-sel
               - ti,am654-phy-gmii-sel
+              - ti,j7200-cpsw5g-phy-gmii-sel
+              - ti,j721e-cpsw9g-phy-gmii-sel
     then:
       properties:
         '#phy-cells':
@@ -88,12 +94,42 @@ allOf:
           description: CPSW port number (starting from 1)
 
   - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,j7200-cpsw5g-phy-gmii-sel
+    then:
+      properties:
+        ti,qsgmii-main-ports:
+          maxItems: 1
+          items:
+            minimum: 1
+            maximum: 4
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,j721e-cpsw9g-phy-gmii-sel
+    then:
+      properties:
+        ti,qsgmii-main-ports:
+          minItems: 2
+          maxItems: 2
+          items:
+            minimum: 1
+            maximum: 8
+
+  - if:
       not:
         properties:
           compatible:
             contains:
               enum:
                 - ti,j7200-cpsw5g-phy-gmii-sel
+                - ti,j721e-cpsw9g-phy-gmii-sel
     then:
       properties:
         ti,qsgmii-main-ports: false