diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-10-04 12:53:28 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-18 11:13:48 -0600 |
| commit | 63fb606a59a4e51572b2f34589b4afd00536f185 (patch) | |
| tree | b93903cd3e727b66e49b7169e4c2d198177ba89f /arch/arm/boot/dts/socfpga.dtsi | |
| parent | 2dbf5494ceec6b70388e16550426a8e65945776b (diff) | |
arm: dts: socfpga: remove "clk-phase" in sdmmc_clk
Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't
need the clk-phase in the sdmmc_clk anymore.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 57a5d6c924b1..1d4a42cef483 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { |