diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-11-08 09:39:30 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2019-11-18 15:50:55 -0600 |
| commit | 68441353538b77dbe7cd94b48d0c3677fb451be0 (patch) | |
| tree | b3901030d76ba616d5a36dd7c32ad8fa50426acb /arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | |
| parent | aa74337ee73df5de3cb6c920100d01c3d95346cc (diff) | |
arm64: dts: agilex: add NAND IP to base dts
Add NAND entry to base DTSI.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/intel/socfpga_agilex.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 94090c6fb946..f9565e76a9d1 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -249,6 +249,18 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; |