diff options
| author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-05-02 10:00:37 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-05-26 19:04:09 -0500 |
| commit | 0cc97d9e3fdf9a7b71b4edfd020a44c54c40df52 (patch) | |
| tree | f2eb8be9e4d6e7a862753a45317e4a15be37233f /arch/arm64/boot/dts/qcom/sm8550-qrd.dts | |
| parent | e7686284066073e3f39b02df0f71db96d7538f48 (diff) | |
arm64: dts: qcom: sm8550: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk
The PCIe Gen4x2 PHY found in the SM8550 SoCs have a second clock named
"PHY_AUX_CLK" which is an input of the Global Clock Controller (GCC) which
is muxed & gated then returned to the PHY as an input.
Remove the dummy pcie-1-phy-aux-clk clock and now the pcie1_phy exposes
2 clocks, properly add the pcie1_phy provided clocks to the Global Clock
Controller (GCC) node clocks inputs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240502-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v5-2-10c650cfeade@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8550-qrd.dts')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 1d487c42a39b..2ed1715000c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -720,17 +720,6 @@ status = "okay"; }; -&gcc { - clocks = <&bi_tcxo_div2>, <&sleep_clk>, - <&pcie0_phy>, - <&pcie1_phy>, - <0>, - <&ufs_mem_phy 0>, - <&ufs_mem_phy 1>, - <&ufs_mem_phy 2>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; -}; - &gpi_dma1 { status = "okay"; }; @@ -809,10 +798,6 @@ data-lanes = <0 1>; }; -&pcie_1_phy_aux_clk { - status = "disabled"; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -906,10 +891,6 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &qupv3_id_0 { status = "okay"; }; |