diff options
| author | Christoph Hellwig <hch@lst.de> | 2021-02-10 10:56:38 +0100 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-02-13 09:51:45 +0100 |
| commit | 14ac09a65e19528ca05df56f8e36a4a8d4949795 (patch) | |
| tree | 87df70b91b37c256417ee8063edec8d82a635dd2 /arch/mips/mti-malta | |
| parent | 3440caf5f28c4e4a585dd5a7cead1b7c414973da (diff) | |
MIPS: refactor the runtime coherent vs noncoherent DMA indicators
Replace the global coherentio enum, and the hw_coherentio (fake) boolean
variables with a single boolean dma_default_coherent flag.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/mti-malta')
| -rw-r--r-- | arch/mips/mti-malta/malta-setup.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 4caff9e3b456..1cdcb76d393e 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -98,7 +98,7 @@ static void __init plat_setup_iocoherency(void) if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; pr_info("Enabled Bonito CPU coherency\n"); - hw_coherentio = 1; + dma_default_coherent = true; } if (strstr(fw_getcmdline(), "iobcuncached")) { BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; @@ -118,12 +118,12 @@ static void __init plat_setup_iocoherency(void) pr_info("CMP IOCU detected\n"); cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU) - hw_coherentio = 1; + dma_default_coherent = true; else pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); } - if (hw_coherentio) + if (dma_default_coherent) pr_info("Hardware DMA cache coherency enabled\n"); else pr_info("Software DMA cache coherency enabled\n"); |