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author | Théo Lebrun <theo.lebrun@bootlin.com> | 2024-06-28 18:11:50 +0200 |
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committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-07-03 17:15:47 +0200 |
commit | bde4b22dc526dea5c1170f2645f268c1d78c924e (patch) | |
tree | 12525b7d90622ba7d28e996a69cd9edc6334c1d3 /arch/mips | |
parent | 02c76df921ae76634933107e082e1c1d00b21120 (diff) |
dt-bindings: soc: mobileye: add EyeQ OLB system controller
Add documentation to describe the "Other Logic Block" system-controller.
It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have
a single instance, whereas EyeQ6H has seven named instances.
Features provided are:
- Clocks, children to main crystal. Some PLLs and divider clocks.
- Resets. Some instances DO NOT have reset.
- Pinctrl. Only EyeQ5 has such feature.
Those are NOT the only features exposed in OLB system-controllers! Many
individual registers, related to IP block integration, can be found.
Additional features will be exposed over time.
We simplify devicetree phandles to OLB in two ways:
- Compatibles exposing a single clock do not ask for a index argument.
This means we use EyeQ6H OLB south (it has four clocks):
clocks = <&olb_south EQ6HC_SOUTH_PLL_PER>;
But use EyeQ6H OLB east (it has one clock):
clocks = <&olb_east>;
- Compatibles exposing a single reset domain do not ask for a domain
index, only a reset index.
This means we use EyeQ5 OLB (it has three domains):
resets = <&olb 0 10>;
But use EyeQ6H west reset (it has one domain):
resets = <&olb_west 3>;
About pinctrl subnodes: all pins have two functionality, either GPIO or
something-else. The latter is pin dependent, we express constraints
using many if-then.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
0 files changed, 0 insertions, 0 deletions