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| author | Catalin Marinas <catalin.marinas@arm.com> | 2021-11-25 15:20:14 +0000 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2021-11-25 15:51:25 +0000 |
| commit | 1f80d15020d7f130194821feb1432b67648c632d (patch) | |
| tree | 867046046dae7913890ee3f734fc84a841431dcb /arch/openrisc | |
| parent | 7183b2b5ae6b8d77a37069566d77cf2a74060f7e (diff) | |
KVM: arm64: Avoid setting the upper 32 bits of TCR_EL2 and CPTR_EL2 to 1
Having a signed (1 << 31) constant for TCR_EL2_RES1 and CPTR_EL2_TCPAC
causes the upper 32-bit to be set to 1 when assigning them to a 64-bit
variable. Bit 32 in TCR_EL2 is no longer RES0 in ARMv8.7: with FEAT_LPA2
it changes the meaning of bits 49:48 and 9:8 in the stage 1 EL2 page
table entries. As a result of the sign-extension, a non-VHE kernel can
no longer boot on a model with ARMv8.7 enabled.
CPTR_EL2 still has the top 32 bits RES0 but we should preempt any future
problems
Make these top bit constants unsigned as per commit df655b75c43f
("arm64: KVM: Avoid setting the upper 32 bits of VTCR_EL2 to 1").
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Chris January <Chris.January@arm.com>
Cc: <stable@vger.kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211125152014.2806582-1-catalin.marinas@arm.com
Diffstat (limited to 'arch/openrisc')
0 files changed, 0 insertions, 0 deletions