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authorAtish Patra <atishp@rivosinc.com>2022-01-20 01:09:16 -0800
committerPalmer Dabbelt <palmer@rivosinc.com>2022-01-20 09:27:11 -0800
commit0b39eb38f85908e039ce8c9f09868438e029757b (patch)
tree2d94289a034f5c2526ce06203d8dbb50a91def7c /arch/riscv
parentc78f94f35cf6486c4057317e8de3ddc4c62e12c7 (diff)
RISC-V: Move the entire hart selection via lottery to SMP
The booting hart selection via lottery is only useful for SMP systems. Moreover, the lottery selection is only necessary for systems using spinwait booting method. It is better to keep the entire lottery selection together so that it can be disabled in future. Move the lottery selection code to under CONFIG_SMP. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/kernel/head.S8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index efa9cd499ac6..b0766f62bd73 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -264,8 +264,8 @@ pmp_done:
blt a0, t0, .Lgood_cores
tail .Lsecondary_park
.Lgood_cores:
-#endif
+ /* The lottery system is only required for spinwait booting method */
#ifndef CONFIG_XIP_KERNEL
/* Pick one hart to run the main boot sequence */
la a3, hart_lottery
@@ -284,6 +284,10 @@ pmp_done:
/* first time here if hart_lottery in RAM is not set */
beq t0, t1, .Lsecondary_start
+#endif /* CONFIG_XIP */
+#endif /* CONFIG_SMP */
+
+#ifdef CONFIG_XIP_KERNEL
la sp, _end + THREAD_SIZE
XIP_FIXUP_OFFSET sp
mv s0, a0
@@ -340,8 +344,8 @@ clear_bss_done:
call soc_early_init
tail start_kernel
-.Lsecondary_start:
#ifdef CONFIG_SMP
+.Lsecondary_start:
/* Set trap vector to spin forever to help debug */
la a3, .Lsecondary_park
csrw CSR_TVEC, a3