diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-07-23 16:17:43 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-07-23 16:17:43 -0700 |
| commit | 4f2d658b2f09c41677871a4285a09cf35f954dad (patch) | |
| tree | ec0a626a598530203871bbc37a340224e5ac87ad /arch | |
| parent | e66d637134b7045ea6f14bdd416cd3695f73ed42 (diff) | |
| parent | 1fc5f7d5c680ac36bd41e13a3d77cbe2eaa312e0 (diff) | |
Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree description updates from Arnd Bergmann:
"This branch contains two kinds of updates: Some platforms in the
process of getting converted to device tree based booting, and the
platform specific patches necessary for that are included here.
Other platforms are already converted, so we just need to update the
actual device tree source files and the binding documents to add
support for new board and new drivers.
In the future we will probably separate those into two branches, and
in the long run, the plan is to move the device tree source files out
of the kernel repository, but that has to wait until we have completed
a much larger portion of the binding documents."
Fix up trivial conflicts in arch/arm/mach-imx/clk-imx6q.c due to newly
added clkdev registers next to a few removed unnecessary ones.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits)
ARM: LPC32xx: Add PWM to base dts file
ARM: EXYNOS: mark the DMA channel binding for SPI as preliminary
ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS5 platforms
ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOS5
ARM: EXYNOS: Add spi clock support for EXYNOS5
ARM: dts: Add nodes for spi controllers for SAMSUNG EXYNOS4 platforms
ARM: EXYNOS: Enable platform support for SPI controllers for EXYNOX4
ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock
ARM: ux500: Remove PMU platform registration when booting with DT
ARM: ux500: Remove temporary snowball_of_platform_devs enablement structure
ARM: ux500: Ensure vendor specific properties have the vendor's identifier
pinctrl: pinctrl-nomadik: Append sleepmode property with vendor specific prefixes
ARM: ux500: Move rtc-pl031 registration to Device Tree when enabled
ARM: ux500: Enable the AB8500 RTC for all DT:ed DB8500 based devices
ARM: ux500: Correctly reference IRQs supplied by the AB8500 from Device Tree
ARM: ux500: Apply ab8500-debug node do the db8500 DT structure
ARM: ux500: Add a ab8500-usb Device Tree node for db8500 based devices
ARM: ux500: Add db8500 Device Tree node for misc/ab8500-pwm
ARM: ux500: Add db8500 Device Tree node for ab8500-sysctrl
ARM: ux500: Enable LED heartbeat functionality on Snowbal via DT
...
Diffstat (limited to 'arch')
93 files changed, 3755 insertions, 473 deletions
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts new file mode 100644 index 000000000000..29b9f15e7599 --- /dev/null +++ b/arch/arm/boot/dts/aks-cdu.dts @@ -0,0 +1,113 @@ +/* + * aks-cdu.dts - Device Tree file for AK signal CDU + * + * Copyright (C) 2012 AK signal Brno a.s. + * 2012 Jiri Prchal <jiri.prchal@aksignal.cz> + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "ge863-pro3.dtsi" + +/ { + chosen { + bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; + }; + + ahb { + apb { + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + usart2: serial@fffb8000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + usart3: serial@fffd0000 { + status = "okay"; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 0>; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 15 0>; + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + bootstrap@0 { + label = "bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "uboot"; + reg = <0x40000 0x80000>; + }; + ubootenv@c0000 { + label = "ubootenv"; + reg = <0xc0000 0x40000>; + }; + kernel@100000 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + rootfs@500000 { + label = "rootfs"; + reg = <0x500000 0x7b00000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + red { + gpios = <&pioC 10 0>; + linux,default-trigger = "none"; + }; + + green { + gpios = <&pioA 5 1>; + linux,default-trigger = "none"; + default-state = "on"; + }; + + yellow { + gpios = <&pioB 20 1>; + linux,default-trigger = "none"; + }; + + blue { + gpios = <&pioB 21 1>; + linux,default-trigger = "none"; + }; + }; +}; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts new file mode 100644 index 000000000000..a9af4db7234c --- /dev/null +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "am33xx.dtsi" + +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts new file mode 100644 index 000000000000..d6a97d9eff72 --- /dev/null +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "am33xx.dtsi" + +/ { + model = "TI AM335x EVM"; + compatible = "ti,am335x-evm", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi new file mode 100644 index 000000000000..59509c48d7e5 --- /dev/null +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -0,0 +1,158 @@ +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,am33xx"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the AM33XX interconnect. + * The real AM33XX interconnect network is quite complex.Since + * that will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <128>; + reg = <0x48200000 0x1000>; + }; + + gpio1: gpio@44e07000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@4804C000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@481AC000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@481AE000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart1: serial@44E09000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@48022000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@48024000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart4: serial@481A6000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + uart5: serial@481A8000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart5"; + clock-frequency = <48000000>; + }; + + uart6: serial@481AA000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart6"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@44E0B000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@4802A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@4819C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + }; +}; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts new file mode 100644 index 000000000000..474f760ecadf --- /dev/null +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap3.dtsi" + +/ { + model = "TI AM3517 EVM (AM3517/05)"; + compatible = "ti,am3517-evm", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index ec2be92b270d..3180a9c588b9 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi @@ -48,7 +48,7 @@ }; rtc@80154000 { - compatible = "stericsson,db8500-rtc"; + compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; interrupts = <0 18 0x4>; }; @@ -60,7 +60,7 @@ interrupts = <0 119 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; @@ -73,7 +73,7 @@ interrupts = <0 120 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; @@ -86,7 +86,7 @@ interrupts = <0 121 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; @@ -99,7 +99,7 @@ interrupts = <0 122 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; @@ -112,7 +112,7 @@ interrupts = <0 123 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <4>; @@ -125,7 +125,7 @@ interrupts = <0 124 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <5>; @@ -138,7 +138,7 @@ interrupts = <0 125 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <6>; @@ -151,7 +151,7 @@ interrupts = <0 126 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <7>; @@ -164,7 +164,7 @@ interrupts = <0 127 0x4>; interrupt-controller; #interrupt-cells = <2>; - supports-sleepmode; + st,supports-sleepmode; gpio-controller; #gpio-cells = <2>; gpio-bank = <8>; @@ -331,6 +331,63 @@ compatible = "stericsson,ab8500"; reg = <5>; /* mailbox 5 is i2c */ interrupts = <0 40 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + + ab8500-rtc { + compatible = "stericsson,ab8500-rtc"; + interrupts = <17 0x4 + 18 0x4>; + interrupt-names = "60S", "ALARM"; + }; + + ab8500-gpadc { + compatible = "stericsson,ab8500-gpadc"; + interrupts = <32 0x4 + 39 0x4>; + interrupt-names = "HW_CONV_END", "SW_CONV_END"; + vddadc-supply = <&ab8500_ldo_tvout_reg>; + }; + + ab8500-usb { + compatible = "stericsson,ab8500-usb"; + interrupts = < 90 0x4 + 96 0x4 + 14 0x4 + 15 0x4 + 79 0x4 + 74 0x4 + 75 0x4>; + interrupt-names = "ID_WAKEUP_R", + "ID_WAKEUP_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_ADP_PROBE_PLUG", + "USB_ADP_PROBE_UNPLUG"; + vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; + v-ape-supply = <&db8500_vape_reg>; + musb_1v8-supply = <&db8500_vsmps2_reg>; + }; + + ab8500-ponkey { + compatible = "stericsson,ab8500-ponkey"; + interrupts = <6 0x4 + 7 0x4>; + interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; + }; + + ab8500-sysctrl { + compatible = "stericsson,ab8500-sysctrl"; + }; + + ab8500-pwm { + compatible = "stericsson,ab8500-pwm"; + }; + + ab8500-debugfs { + compatible = "stericsson,ab8500-debug"; + }; ab8500-regulators { compatible = "stericsson,ab8500-regulator"; diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index c07ba8c2cc0d..d79b28d9c963 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -152,6 +152,23 @@ uart1: serial@40014000 { status = "okay"; }; + + /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ + adc@40048000 { + status = "okay"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@21 { + label = "GPIO Key UP"; + linux,code = <103>; + gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; }; }; diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts new file mode 100644 index 000000000000..b7354e6506de --- /dev/null +++ b/arch/arm/boot/dts/evk-pro3.dts @@ -0,0 +1,41 @@ +/* + * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 + * + * Copyright (C) 2012 Telit, + * 2012 Fabio Porcedda <fabio.porcedda@gmail.com> + * + * Licensed under GPLv2 or later. + */ + +/dts-v1/; + +/include/ "ge863-pro3.dtsi" + +/ { + model = "Telit EVK-PRO3 for Telit GE863-PRO3"; + compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; + + ahb { + apb { + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 0>; + status = "okay"; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c@0 { + status = "okay"; + }; + +};
\ No newline at end of file diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index b8c476384eef..0c49caa09978 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -134,4 +134,16 @@ i2c@138D0000 { status = "disabled"; }; + + spi_0: spi@13920000 { + status = "disabled"; + }; + + spi_1: spi@13930000 { + status = "disabled"; + }; + + spi_2: spi@13940000 { + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 27afc8e535ca..1beccc8f14ff 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -179,4 +179,42 @@ i2c@138D0000 { status = "disabled"; }; + + spi_0: spi@13920000 { + status = "disabled"; + }; + + spi_1: spi@13930000 { + status = "disabled"; + }; + + spi_2: spi@13940000 { + gpios = <&gpc1 1 5 3 0>, + <&gpc1 3 5 3 0>, + <&gpc1 4 5 3 0>; + + w25x80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + cs-gpio = <&gpc1 2 1 0 3>; + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index a1dd2ee83753..02891fe876e4 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -25,6 +25,12 @@ compatible = "samsung,exynos4210"; interrupt-parent = <&gic>; + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + gic:interrupt-controller@10490000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -33,6 +39,17 @@ reg = <0x10490000 0x1000>, <0x10480000 0x100>; }; + combiner:interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x10440000 0x1000>; + interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, + <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, + <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, + <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; + }; + watchdog@10060000 { compatible = "samsung,s3c2410-wdt"; reg = <0x10060000 0x100>; @@ -147,6 +164,36 @@ interrupts = <0 65 0>; }; + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 7>; /* preliminary */ + rx-dma-channel = <&pdma0 6>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 67 0>; + tx-dma-channel = <&pdma1 7>; /* preliminary */ + rx-dma-channel = <&pdma1 6>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = <0 68 0>; + tx-dma-channel = <&pdma0 9>; /* preliminary */ + rx-dma-channel = <&pdma0 8>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + amba { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49945cc1bc7d..8a5e348793c7 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -71,4 +71,42 @@ i2c@12CD0000 { status = "disabled"; }; + + spi_0: spi@12d20000 { + status = "disabled"; + }; + + spi_1: spi@12d30000 { + gpios = <&gpa2 4 2 3 0>, + <&gpa2 6 2 3 0>, + <&gpa2 7 2 3 0>; + + w25q80bw@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + cs-gpio = <&gpa2 5 1 0 3>; + samsung,spi-feedback-delay = <0>; + }; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; + }; + }; + }; + + spi_2: spi@12d40000 { + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 4272b2949228..004aaa8d123c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -23,6 +23,12 @@ compatible = "samsung,exynos5250"; interrupt-parent = <&gic>; + aliases { + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + gic:interrupt-controller@10481000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -146,6 +152,36 @@ #size-cells = <0>; }; + spi_0: spi@12d20000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d20000 0x100>; + interrupts = <0 66 0>; + tx-dma-channel = <&pdma0 5>; /* preliminary */ + rx-dma-channel = <&pdma0 4>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_1: spi@12d30000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d30000 0x100>; + interrupts = <0 67 0>; + tx-dma-channel = <&pdma1 5>; /* preliminary */ + rx-dma-channel = <&pdma1 4>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_2: spi@12d40000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x12d40000 0x100>; + interrupts = <0 68 0>; + tx-dma-channel = <&pdma0 7>; /* preliminary */ + rx-dma-channel = <&pdma0 6>; /* preliminary */ + #address-cells = <1>; + #size-cells = <0>; + }; + amba { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi new file mode 100644 index 000000000000..17136fc7a516 --- /dev/null +++ b/arch/arm/boot/dts/ge863-pro3.dtsi @@ -0,0 +1,52 @@ +/* + * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 + * + * Copyright (C) 2012 Telit, + * 2012 Fabio Porcedda <fabio.porcedda@gmail.com> + * + * Licensed under GPLv2 or later. + */ + +/include/ "at91sam9260.dtsi" + +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <6000000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + boot@0 { + label = "boot"; + reg = <0x0 0x7c0000>; + }; + + root@07c0000 { + label = "root"; + reg = <0x7c0000 0x7840000>; + }; + }; + }; + + chosen { + bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; + }; +}; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 70bffa929b65..e3486f486b40 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -22,17 +22,60 @@ apb@80000000 { apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; + status = "okay"; + }; + ssp0: ssp@80010000 { compatible = "fsl,imx23-mmc"; pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>; - bus-width = <8>; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>; + panel-enable-gpios = <&gpio1 18 0>; status = "okay"; }; }; apbx@80040000 { + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + duart: serial@80070000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; @@ -40,4 +83,23 @@ }; }; }; + + regulators { + compatible = "simple-bus"; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; }; diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts new file mode 100644 index 000000000000..20912b1d8893 --- /dev/null +++ b/arch/arm/boot/dts/imx23-olinuxino.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx23.dtsi" + +/ { + model = "i.MX23 Olinuxino Low Cost Board"; + compatible = "olimex,imx23-olinuxino", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + status = "okay"; + }; + }; + + apbx@80040000 { + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts new file mode 100644 index 000000000000..757a327ff3e8 --- /dev/null +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts @@ -0,0 +1,78 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx23.dtsi" + +/ { + model = "Freescale STMP378x Development Board"; + compatible = "fsl,stmp378x-devb", "fsl,imx23"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; + bus-width = <4>; + wp-gpios = <&gpio1 30 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ + 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 8c5f9994f3fc..a874dbfb5ae6 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -18,6 +18,8 @@ gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; + serial0 = &auart0; + serial1 = &auart1; }; cpus { @@ -57,13 +59,15 @@ status = "disabled"; }; - bch@8000a000 { - reg = <0x8000a000 2000>; - status = "disabled"; - }; - - gpmi@8000c000 { - reg = <0x8000c000 2000>; + gpmi-nand@8000c000 { + compatible = "fsl,imx23-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 2000>, <0x8000a000 2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <13>, <56>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -114,24 +118,151 @@ duart_pins_a: duart@0 { reg = <0>; - fsl,pinmux-ids = <0x11a2 0x11b2>; + fsl,pinmux-ids = < + 0x11a2 /* MX23_PAD_PWM0__DUART_RX */ + 0x11b2 /* MX23_PAD_PWM1__DUART_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */ + 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */ + 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */ + 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; }; + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */ + 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */ + 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */ + 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */ + 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */ + 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */ + 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */ + 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */ + 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */ + 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */ + 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */ + 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */ + 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ + 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ + 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ + 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_pins_fixup: gpmi-pins-fixup { + fsl,pinmux-ids = < + 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ + 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ + 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ + >; + fsl,drive-strength = <2>; + }; + + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ + 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ + 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ + 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ + 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; - fsl,pinmux-ids = <0x2020 0x2030 0x2040 - 0x2050 0x0082 0x0092 0x00a2 - 0x00b2 0x2000 0x2010 0x2060>; + fsl,pinmux-ids = < + 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ + 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ + 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ + 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ + 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */ + 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */ + 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */ + 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */ + 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; }; mmc0_pins_fixup: mmc0-pins-fixup { - fsl,pinmux-ids = <0x2010 0x2060>; + fsl,pinmux-ids = < + 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ + 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ + >; + fsl,pull-up = <0>; + }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11c0 /* MX23_PAD_PWM2__PWM2 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */ + 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */ + 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */ + 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */ + 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */ + 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */ + 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */ + 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */ + 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */ + 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */ + 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; fsl,pull-up = <0>; }; }; @@ -172,7 +303,9 @@ }; lcdif@80030000 { + compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; + interrupts = <46 45>; status = "disabled"; }; @@ -242,12 +375,16 @@ }; rtc@8005c000 { + compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; reg = <0x8005c000 2000>; - status = "disabled"; + interrupts = <22>; }; - pwm@80064000 { + pwm: pwm@80064000 { + compatible = "fsl,imx23-pwm"; reg = <0x80064000 2000>; + #pwm-cells = <2>; + fsl,pwm-number = <5>; status = "disabled"; }; @@ -257,12 +394,16 @@ }; auart0: serial@8006c000 { + compatible = "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; + interrupts = <24 25 23>; status = "disabled"; }; auart1: serial@8006e000 { + compatible = "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; + interrupts = <59 60 58>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts new file mode 100644 index 000000000000..d3f8296e19e0 --- /dev/null +++ b/arch/arm/boot/dts/imx27-3ds.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx27.dtsi" + +/ { + model = "mx27_3ds"; + compatible = "freescale,imx27-3ds", "fsl,imx27"; + + memory { + reg = <0x0 0x0>; + }; + + soc { + aipi@10000000 { /* aipi */ + + wdog@10002000 { + status = "okay"; + }; + + uart@1000a000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + + fec@1002b000 { + status = "okay"; + }; + }; + }; + +}; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 386c769c38d1..00bae3aad5ab 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -121,7 +121,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@10015100 { @@ -131,7 +131,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@10015200 { @@ -141,7 +141,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@10015300 { @@ -151,7 +151,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio5: gpio@10015400 { @@ -161,7 +161,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio6: gpio@10015500 { @@ -171,7 +171,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; cspi3: cspi@10017000 { diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts new file mode 100644 index 000000000000..b383417a558f --- /dev/null +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -0,0 +1,198 @@ +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Bluegiga APX4 Development Kit"; + compatible = "bluegiga,apx4devkit", "fsl,imx28"; + + memory { + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + + ssp2: ssp@80014000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; + bus-width = <4>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ + 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ + 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ + 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_apx4: lcdif-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ + 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ + 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ + 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { + fsl,pinmux-ids = < + 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ + >; + fsl,drive-strength = <2>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_apx4>; + status = "okay"; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; + }; + + saif1: saif@80046000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; + }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; + }; + + auart2: serial@8006e000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "bluegiga,apx4devkit-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "apx4devkit-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio3 28 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts new file mode 100644 index 000000000000..c03a577beca3 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -0,0 +1,52 @@ +/* + * Copyright 2012 Free Electrons + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Crystalfontz CFA-10036 Board"; + compatible = "crystalfontz,cfa10036", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + }; + + apbx@80040000 { + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&gpio3 4 1>; + default-state = "on"; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index ee520a529cb4..773c0e84d1fb 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -22,6 +22,13 @@ apb@80000000 { apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg + &gpmi_pins_evk>; + status = "okay"; + }; + ssp0: ssp@80010000 { compatible = "fsl,imx28-mmc"; pinctrl-names = "default"; @@ -29,6 +36,7 @@ &mmc0_cd_cfg &mmc0_sck_cfg>; bus-width = <8>; wp-gpios = <&gpio2 12 0>; + vmmc-supply = <®_vddio_sd0>; status = "okay"; }; @@ -36,6 +44,72 @@ compatible = "fsl,imx28-mmc"; bus-width = <8>; wp-gpios = <&gpio0 28 0>; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ + 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */ + 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */ + 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ + 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ + 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ + 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ + 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_pins_evk: gpmi-nand-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ + 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_evk: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_evk>; + panel-enable-gpios = <&gpio3 30 0>; + status = "okay"; + }; + + can0: can@80032000 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; + }; + + can1: can@80034000 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; status = "okay"; }; }; @@ -68,19 +142,58 @@ }; }; + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; + }; + duart: serial@80074000 { pinctrl-names = "default"; pinctrl-0 = <&duart_pins_a>; status = "okay"; }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; }; }; ahb@80080000 { + usb0: usb@80080000 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; + }; + + usb1: usb@80090000 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + mac0: ethernet@800f0000 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 13 0>; + phy-reset-duration = <100>; status = "okay"; }; @@ -102,6 +215,40 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_vddio_sd0: vddio-sd0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; + + reg_fec_3v3: fec-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 15 0>; + }; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 9 0>; + enable-active-high; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 8 0>; + enable-active-high; + }; }; sound { @@ -111,4 +258,21 @@ saif-controllers = <&saif0 &saif1>; audio-codec = <&sgtl5000>; }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio3 5 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 2 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; }; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts new file mode 100644 index 000000000000..183a3fd2d859 --- /dev/null +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "DENX M28EVK"; + compatible = "denx,m28evk", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + gpmi-nand@8000c000 { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x00300000>; + read-only; + }; + + partition@1 { + label = "environment"; + reg = <0x00300000 0x00080000>; + }; + + partition@2 { + label = "redundant-environment"; + reg = <0x00380000 0x00080000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x00400000 0x00400000>; + }; + + partition@4 { + label = "filesystem"; + reg = <0x00800000 0x0f800000>; + }; + }; + + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio3 10 1>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ + 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ + 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + status = "okay"; + }; + + can0: can@80032000 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; + }; + + can1: can@80034000 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; + }; + + saif1: saif@80046000 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; + }; + + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + }; + + eeprom: eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "stm,mt41t62"; + reg = <0x68>; + }; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006a000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + auart3: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio3 11 0>; + status = "okay"; + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "denx,m28evk-sgtl5000", + "fsl,mxs-audio-sgtl5000"; + model = "m28evk-sgtl5000"; + saif-controllers = <&saif0 &saif1>; + audio-codec = <&sgtl5000>; + }; +}; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts new file mode 100644 index 000000000000..62bf767409a6 --- /dev/null +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -0,0 +1,97 @@ +/dts-v1/; +/include/ "imx28.dtsi" + +/ { + model = "Ka-Ro electronics TX28 module"; + compatible = "karo,tx28", "fsl,imx28"; + + memory { + reg = <0x40000000 0x08000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + }; + + apbx@80040000 { + i2c0: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "mxim,ds1339"; + reg = <0x68>; + }; + }; + + pwm: pwm@80064000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; + }; + + duart: serial@80074000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + status = "okay"; + }; + + auart1: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; + }; + }; + }; + + ahb@80080000 { + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio4 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; +}; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 4634cb861a59..915db89e3644 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -22,6 +22,11 @@ gpio4 = &gpio4; saif0 = &saif0; saif1 = &saif1; + serial0 = &auart0; + serial1 = &auart1; + serial2 = &auart2; + serial3 = &auart3; + serial4 = &auart4; }; cpus { @@ -68,15 +73,15 @@ status = "disabled"; }; - bch@8000a000 { - reg = <0x8000a000 2000>; - interrupts = <41>; - status = "disabled"; - }; - - gpmi@8000c000 { - reg = <0x8000c000 2000>; - interrupts = <42 88>; + gpmi-nand@8000c000 { + compatible = "fsl,imx28-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 2000>, <0x8000a000 2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <88>, <41>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <4>; status = "disabled"; }; @@ -161,7 +166,150 @@ duart_pins_a: duart@0 { reg = <0>; - fsl,pinmux-ids = <0x3102 0x3112>; + fsl,pinmux-ids = < + 0x3102 /* MX28_PAD_PWM0__DUART_RX */ + 0x3112 /* MX28_PAD_PWM1__DUART_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + duart_pins_b: duart@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + duart_4pins_a: duart-4pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ + 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ + 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ + 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ + 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ + 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ + 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ + 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ + 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ + 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ + 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ + 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_status_cfg: gpmi-status-cfg { + fsl,pinmux-ids = < + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + >; + fsl,drive-strength = <2>; + }; + + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ + 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart1_pins_a: auart1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ + 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart2_2pins_a: auart2-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ + 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart3_pins_a: auart3@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ + 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ + 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ + 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart3_2pins_a: auart3-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ + 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ + >; fsl,drive-strength = <0>; fsl,voltage = <1>; fsl,pull-up = <0>; @@ -169,9 +317,17 @@ mac0_pins_a: mac0@0 { reg = <0>; - fsl,pinmux-ids = <0x4000 0x4010 0x4020 - 0x4030 0x4040 0x4060 0x4070 - 0x4080 0x4100>; + fsl,pinmux-ids = < + 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ + 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ + 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ + 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ + 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ + 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ + 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ + 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ + 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -179,8 +335,14 @@ mac1_pins_a: mac1@0 { reg = <0>; - fsl,pinmux-ids = <0x40f1 0x4091 0x40a1 - 0x40e1 0x40b1 0x40c1>; + fsl,pinmux-ids = < + 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ + 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ + 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ + 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ + 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ + 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -188,28 +350,61 @@ mmc0_8bit_pins_a: mmc0-8bit@0 { reg = <0>; - fsl,pinmux-ids = <0x2000 0x2010 0x2020 - 0x2030 0x2040 0x2050 0x2060 - 0x2070 0x2080 0x2090 0x20a0>; + fsl,pinmux-ids = < + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ + 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ + 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ + 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; }; mmc0_cd_cfg: mmc0-cd-cfg { - fsl,pinmux-ids = <0x2090>; + fsl,pinmux-ids = < + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + >; fsl,pull-up = <0>; }; mmc0_sck_cfg: mmc0-sck-cfg { - fsl,pinmux-ids = <0x20a0>; + fsl,pinmux-ids = < + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; fsl,drive-strength = <2>; fsl,pull-up = <0>; }; i2c0_pins_a: i2c0@0 { reg = <0>; - fsl,pinmux-ids = <0x3180 0x3190>; + fsl,pinmux-ids = < + 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ + 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ + >; fsl,drive-strength = <1>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -217,8 +412,12 @@ saif0_pins_a: saif0@0 { reg = <0>; - fsl,pinmux-ids = - <0x3140 0x3150 0x3160 0x3170>; + fsl,pinmux-ids = < + 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ + 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ + 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ + 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ + >; fsl,drive-strength = <2>; fsl,voltage = <1>; fsl,pull-up = <1>; @@ -226,11 +425,88 @@ saif1_pins_a: saif1@0 { reg = <0>; - fsl,pinmux-ids = <0x31a0>; + fsl,pinmux-ids = < + 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ + >; fsl,drive-strength = <2>; fsl,voltage = <1>; fsl,pull-up = <1>; }; + + pwm0_pins_a: pwm0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3100 /* MX28_PAD_PWM0__PWM_0 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3120 /* MX28_PAD_PWM2__PWM_2 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ + 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ + 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ + 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ + 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ + 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + can0_pins_a: can0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ + 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + can1_pins_a: can1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ + 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; }; digctl@8001c000 { @@ -272,18 +548,21 @@ }; lcdif@80030000 { + compatible = "fsl,imx28-lcdif"; reg = <0x80030000 2000>; interrupts = <38 86>; status = "disabled"; }; can0: can@80032000 { + compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80032000 2000>; interrupts = <8>; status = "disabled"; }; can1: can@80034000 { + compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; reg = <0x80034000 2000>; interrupts = <9>; status = "disabled"; @@ -370,9 +649,9 @@ }; rtc@80056000 { + compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; reg = <0x80056000 2000>; - interrupts = <28 29>; - status = "disabled"; + interrupts = <29>; }; i2c0: i2c@80058000 { @@ -393,8 +672,11 @@ status = "disabled"; }; - pwm@80064000 { + pwm: pwm@80064000 { + compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; reg = <0x80064000 2000>; + #pwm-cells = <2>; + fsl,pwm-number = <8>; status = "disabled"; }; @@ -404,30 +686,35 @@ }; auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006a000 0x2000>; interrupts = <112 70 71>; status = "disabled"; }; auart1: serial@8006c000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006c000 0x2000>; interrupts = <113 72 73>; status = "disabled"; }; auart2: serial@8006e000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x8006e000 0x2000>; interrupts = <114 74 75>; status = "disabled"; }; auart3: serial@80070000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80070000 0x2000>; interrupts = <115 76 77>; status = "disabled"; }; auart4: serial@80072000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; reg = <0x80072000 0x2000>; interrupts = <116 78 79>; status = "disabled"; @@ -441,11 +728,13 @@ }; usbphy0: usbphy@8007c000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007c000 0x2000>; status = "disabled"; }; usbphy1: usbphy@8007e000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; reg = <0x8007e000 0x2000>; status = "disabled"; }; @@ -459,13 +748,19 @@ reg = <0x80080000 0x80000>; ranges; - usbctrl0: usbctrl@80080000 { + usb0: usb@80080000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80080000 0x10000>; + interrupts = <93>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; - usbctrl1: usbctrl@80090000 { + usb1: usb@80090000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; reg = <0x80090000 0x10000>; + interrupts = <92>; + fsl,usbphy = <&usbphy1>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts new file mode 100644 index 000000000000..24731cb78e8e --- /dev/null +++ b/arch/arm/boot/dts/imx31-bug.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "imx31.dtsi" + +/ { + model = "Buglabs i.MX31 Bug 1.x"; + compatible = "fsl,imx31-bug", "fsl,imx31"; + + memory { + reg = <0x80000000 0x8000000>; /* 128M */ + }; + + soc { + aips@43f00000 { /* AIPS1 */ + uart5: serial@43fb4000 { + fsl,uart-has-rtscts; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi new file mode 100644 index 000000000000..eef7099f3e3c --- /dev/null +++ b/arch/arm/boot/dts/imx31.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + avic: avic-interrupt-controller@60000000 { + compatible = "fsl,imx31-avic", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x60000000 0x100000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&avic>; + ranges; + + aips@43f00000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x43f00000 0x100000>; + ranges; + + uart1: serial@43f90000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + status = "disabled"; + }; + + uart2: serial@43f94000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f94000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + + uart4: serial@43fb0000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43fb0000 0x4000>; + interrupts = <46>; + status = "disabled"; + }; + + uart5: serial@43fb4000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43fb4000 0x4000>; + interrupts = <47>; + status = "disabled"; + }; + }; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x100000>; + ranges; + + uart3: serial@5000c000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <18>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index bfa65abe8ef2..922adefdd291 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -133,7 +133,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@73f88000 { @@ -143,7 +143,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@73f8c000 { @@ -153,7 +153,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@73f90000 { @@ -163,7 +163,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; wdog@73f98000 { /* WDOG1 */ diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index e3e869470cd3..4e735edc78ed 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -135,7 +135,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@53f88000 { @@ -145,7 +145,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@53f8c000 { @@ -155,7 +155,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@53f90000 { @@ -165,7 +165,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; wdog@53f98000 { /* WDOG1 */ @@ -203,7 +203,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio6: gpio@53fe0000 { @@ -213,7 +213,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio7: gpio@53fe4000 { @@ -223,7 +223,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; i2c@53fec000 { /* I2C3 */ diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index db4c6096c562..d792581672cc 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -22,6 +22,12 @@ }; soc { + gpmi-nand@00112000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* gpmi nand conflicts with SD */ + }; + aips-bus@02100000 { /* AIPS2 */ ethernet@02188000 { phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index e0ec92973e7e..d42e851ceb97 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -27,6 +27,8 @@ ecspi@02008000 { /* eCSPI1 */ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; status = "okay"; flash: m25p80@0 { @@ -42,9 +44,31 @@ }; }; + iomuxc@020e0000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hog>; + + gpios { + pinctrl_gpio_hog: gpiohog { + fsl,pins = < + 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ + >; + }; + }; + }; }; aips-bus@02100000 { /* AIPS2 */ + usb@02184000 { /* USB OTG */ + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; + }; + + usb@02184200 { /* USB1 */ + status = "okay"; + }; + ethernet@02188000 { phy-mode = "rgmii"; phy-reset-gpios = <&gpio3 23 0>; @@ -111,6 +135,15 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_usb_otg_vbus: usb_otg_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; }; sound { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 8c90cbac945f..c25d49584814 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -87,6 +87,23 @@ interrupt-parent = <&intc>; ranges; + dma-apbh@00110000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x00110000 0x2000>; + }; + + gpmi-nand@00112000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; + }; + timer@00a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -266,7 +283,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio2: gpio@020a0000 { @@ -276,7 +293,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio3: gpio@020a4000 { @@ -286,7 +303,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio4: gpio@020a8000 { @@ -296,7 +313,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio5: gpio@020ac000 { @@ -306,7 +323,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio6: gpio@020b0000 { @@ -316,7 +333,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; gpio7: gpio@020b4000 { @@ -326,7 +343,7 @@ gpio-controller; #gpio-cells = <2>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; }; kpp@020b8000 { @@ -444,12 +461,14 @@ }; }; - usbphy@020c9000 { /* USBPHY1 */ + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; }; - usbphy@020ca000 { /* USBPHY2 */ + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; }; @@ -495,6 +514,30 @@ }; }; + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + }; + }; + i2c1 { pinctrl_i2c1_1: i2c1grp-1 { fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ @@ -538,6 +581,14 @@ 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ }; }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + }; + }; }; dcic@020e4000 { /* DCIC1 */ @@ -573,6 +624,36 @@ reg = <0x0217c000 0x4000>; }; + usb@02184000 { /* USB OTG */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 0x04>; + fsl,usbphy = <&usbphy1>; + status = "disabled"; + }; + + usb@02184200 { /* USB1 */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <0 40 0x04>; + fsl,usbphy = <&usbphy2>; + status = "disabled"; + }; + + usb@02184400 { /* USB2 */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 41 0x04>; + status = "disabled"; + }; + + usb@02184600 { /* USB3 */ + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184600 0x200>; + interrupts = <0 42 0x04>; + status = "disabled"; + }; + ethernet@02188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c5f37fbd33e6..e5ffe960dbf3 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -278,6 +278,11 @@ status = "disabled"; }; + pwm: pwm@4005C000 { + compatible = "nxp,lpc3220-pwm"; + reg = <0x4005C000 0x8>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts new file mode 100644 index 000000000000..25b50b759dec --- /dev/null +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap2.dtsi" + +/ { + model = "TI OMAP2420 H4 board"; + compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x84000000>; /* 64 MB */ + }; +}; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 2eee16ec59b4..f349ee9182ce 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -18,3 +18,31 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; }; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; +}; + +/include/ "twl4030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * TVP5146 Video decoder-in for analog input support. + */ + tvp5146@5c { + compatible = "ti,tvp5146m2"; + reg = <0x5c>; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 99474fa5fac4..810947198208 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -215,5 +215,10 @@ compatible = "ti,omap3-hsmmc"; ti,hwmods = "mmc3"; }; + + wdt2: wdt@48314000 { + compatible = "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; + }; }; }; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 9d8abf0938e0..9880c12877b3 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -32,6 +32,30 @@ linux,default-trigger = "mmc0"; }; }; + + sound: sound { + compatible = "ti,abe-twl6040"; + ti,model = "PandaBoard"; + + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "AFML", "Line In", + "AFMR", "Line In"; + }; }; &i2c1 { @@ -43,6 +67,19 @@ interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + }; }; /include/ "twl6030.dtsi" diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-pandaES.dts new file mode 100644 index 000000000000..d4ba43a48d9b --- /dev/null +++ b/arch/arm/boot/dts/omap4-pandaES.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/include/ "omap4-panda.dts" + +/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ +&sound { + ti,model = "PandaBoardES"; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "AFML", "Line In", + "AFMR", "Line In"; +}; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 9b1c13a16c2c..72216e932fc0 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -28,6 +28,14 @@ regulator-boot-on; }; + vbat: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + regulator-min-microvolt = <3750000>; + regulator-max-microvolt = <3750000>; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; debug0 { @@ -70,6 +78,41 @@ gpios = <&gpio5 11 0>; /* 139 */ }; }; + + sound { + compatible = "ti,abe-twl6040"; + ti,model = "SDP4430"; + + ti,jack-detection = <1>; + ti,mclk-freq = <38400000>; + + ti,mcpdm = <&mcpdm>; + ti,dmic = <&dmic>; + + ti,twl6040 = <&twl6040>; + + /* Audio routing */ + ti,audio-routing = + "Headset Stereophone", "HSOL", + "Headset Stereophone", "HSOR", + "Earphone Spk", "EP", + "Ext Spk", "HFL", + "Ext Spk", "HFR", + "Line Out", "AUXL", + "Line Out", "AUXR", + "Vibrator", "VIBRAL", + "Vibrator", "VIBRAR", + "HSMIC", "Headset Mic", + "Headset Mic", "Headset Mic Bias", + "MAINMIC", "Main Handset Mic", + "Main Handset Mic", "Main Mic Bias", + "SUBMIC", "Sub Handset Mic", + "Sub Handset Mic", "Main Mic Bias", + "AFML", "Line In", + "AFMR", "Line In", + "DMic", "Digital Mic", + "Digital Mic", "Digital Mic1 Bias"; + }; }; &i2c1 { @@ -81,6 +124,31 @@ interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ interrupt-parent = <&gic>; }; + + twl6040: twl@4b { + compatible = "ti,twl6040"; + reg = <0x4b>; + /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ + interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ + interrupt-parent = <&gic>; + ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ + + vio-supply = <&v1v8>; + v2v1-supply = <&v2v1>; + enable-active-high; + + /* regulators for vibra motor */ + vddvibl-supply = <&vbat>; + vddvibr-supply = <&vbat>; + + vibra { + /* Vibra driver, motor resistance parameters */ + ti,vibldrv-res = <8>; + ti,vibrdrv-res = <3>; + ti,viblmotor-res = <10>; + ti,vibrmotor-res = <10>; + }; + }; }; /include/ "twl6030.dtsi" diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts new file mode 100644 index 000000000000..6601e6af6092 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var_som.dts @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +/include/ "omap4.dtsi" + +/ { + model = "Variscite OMAP4 SOM"; + compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + vdd_eth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "VDD_ETH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; + }; +}; + +/include/ "twl6030.dtsi" + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; + + /* + * Temperature Sensor + * http://www.ti.com/lit/ds/symlink/tmp105.pdf + */ + tmp105@49 { + compatible = "ti,tmp105"; + reg = <0x49>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; +}; + +&mcspi1 { + eth@0 { + compatible = "ks8851"; + spi-max-frequency = <24000000>; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <11>; /* gpio line 171 */ + vdd-supply = <&vdd_eth>; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc>; + ti,bus-width = <8>; + ti,non-removable; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + ti,bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 359c4979c8aa..04cbbcb6ff91 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -272,5 +272,28 @@ ti,hwmods = "mmc5"; ti,needs-special-reset; }; + + wdt2: wdt@4a314000 { + compatible = "ti,omap4-wdt", "ti,omap3-wdt"; + ti,hwmods = "wd_timer2"; + }; + + mcpdm: mcpdm@40132000 { + compatible = "ti,omap4-mcpdm"; + reg = <0x40132000 0x7f>, /* MPU private access */ + <0x49032000 0x7f>; /* L3 Interconnect */ + interrupts = <0 112 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "mcpdm"; + }; + + dmic: dmic@4012e000 { + compatible = "ti,omap4-dmic"; + reg = <0x4012e000 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + interrupts = <0 114 0x4>; + interrupt-parent = <&gic>; + ti,hwmods = "dmic"; + }; }; }; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index ec3c33975110..7e334d4cae21 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -77,6 +77,8 @@ used-led { label = "user_led"; gpios = <&gpio4 14 0x4>; + default-state = "on"; + linux,default-trigger = "heartbeat"; }; }; @@ -101,15 +103,30 @@ }; }; + // External Micro SD slot sdi@80126000 { - status = "enabled"; + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; + + #gpio-cells = <1>; cd-gpios = <&gpio6 26 0x4>; // 218 + cd-inverted; + + status = "okay"; }; + // On-board eMMC sdi@80114000 { - status = "enabled"; + arm,primecell-periphid = <0x10480180>; + max-frequency = <50000000>; + bus-width = <8>; + mmc-cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux2_reg>; + + status = "okay"; }; uart@80120000 { diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index b797901d040d..85e621ab2968 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -64,11 +64,6 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; - ddc { - nvidia,pins = "ddc", "owc", "spdi", "spdo", - "uac"; - nvidia,function = "rsvd2"; - }; dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; nvidia,function = "vi"; @@ -129,14 +124,14 @@ "lspi", "lvp1", "lvs"; nvidia,function = "displaya"; }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; }; - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; rm { nvidia,pins = "rm"; nvidia,function = "i2c1"; @@ -176,7 +171,7 @@ conf_ata { nvidia,pins = "ata", "atb", "atc", "atd", "cdev1", "cdev2", "dap1", "dap2", - "dap4", "dtf", "gma", "gmc", "gmd", + "dap4", "ddc", "dtf", "gma", "gmc", "gmd", "gme", "gpu", "gpu7", "i2cp", "irrx", "irtx", "pta", "rm", "sdc", "sdd", "slxd", "slxk", "spdi", "spdo", "uac", @@ -185,7 +180,7 @@ nvidia,tristate = <0>; }; conf_ate { - nvidia,pins = "ate", "csus", "dap3", "ddc", + nvidia,pins = "ate", "csus", "dap3", "gpv", "owc", "slxc", "spib", "spid", "spie"; nvidia,pull = <0>; @@ -255,6 +250,39 @@ nvidia,slew-rate-falling = <3>; }; }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; }; i2s@70002800 { @@ -303,12 +331,37 @@ i2c@7000c400 { status = "okay"; clock-frequency = <100000>; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; - smart-battery@b { - compatible = "ti,bq20z75", "smart-battery-1.1"; - reg = <0xb>; - ti,i2c-retry-count = <2>; - ti,poll-retry-count = <10>; + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "smart-battery-1.1"; + reg = <0xb>; + ti,i2c-retry-count = <2>; + ti,poll-retry-count = <10>; + }; }; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts new file mode 100644 index 000000000000..6916310bf58f --- /dev/null +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -0,0 +1,301 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atb", "ate", "gma", "gmb", + "gmc", "gmd", "gpu"; + nvidia,function = "gmi"; + }; + atc { + nvidia,pins = "atc", "atd"; + nvidia,function = "sdio4"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "osc"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,function = "vi"; + }; + dte { + nvidia,pins = "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gme { + nvidia,pins = "gme"; + nvidia,function = "dap5"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + kbcb { + nvidia,pins = "kbcb", "kbcd"; + nvidia,function = "sdio2"; + }; + lcsn { + nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", + "spia", "spib", "spic"; + nvidia,function = "spi3"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldc", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", "lm0", + "lm1", "lpp", "lpw0", "lpw1", "lpw2", + "lsc0", "lsc1", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "uac"; + nvidia,function = "owr"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxa", + "slxc", "slxd", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + spdi { + nvidia,pins = "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + spid { + nvidia,pins = "spid", "spie", "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + spif { + nvidia,pins = "spif"; + nvidia,function = "spi2"; + }; + uaa { + nvidia,pins = "uaa", "uab"; + nvidia,function = "uarta"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + uda { + nvidia,pins = "uda"; + nvidia,function = "spi1"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "ddc", "gma", + "gmb", "gmc", "gmd", "irrx", "irtx", + "kbca", "kbcb", "kbcc", "kbcd", "kbce", + "kbcf", "sdc", "sdd", "spie", "spig", + "spih", "uaa", "uab", "uad", "uca", + "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_atd { + nvidia,pins = "atd", "ate", "cdev1", "csus", + "dap1", "dap2", "dap3", "dap4", "dte", + "dtf", "gpu", "gpu7", "gpv", "i2cp", + "rm", "sdio1", "slxa", "slxc", "slxd", + "slxk", "spdi", "spdo", "uac", "uda"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_cdev2 { + nvidia,pins = "cdev2", "spia", "spib"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "lc", "pmca", + "pmcb", "pmcc", "pmcd", "xm2c", + "xm2d"; + nvidia,pull = <0>; + }; + conf_crtp { + nvidia,pins = "crtp"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <0>; + }; + conf_gme { + nvidia,pins = "gme", "owc", "pta", "spic"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + conf_ls { + nvidia,pins = "ls", "pmce"; + nvidia,pull = <2>; + }; + drive_dap1 { + nvidia,pins = "drive_dap1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <1>; + nvidia,low-power-mode = <0>; + nvidia,pull-down-strength = <0>; + nvidia,pull-up-strength = <0>; + nvidia,slew-rate-rising = <0>; + nvidia,slew-rate-falling = <0>; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006000 { + status = "okay"; + clock-frequency = <216000000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + codec: codec@1a { + compatible = "wlf,wm8753"; + reg = <0x1a>; + }; + + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + usb@c5000000 { + status = "okay"; + nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ + }; + + usb@c5008000 { + status = "okay"; + nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ + }; + + sdhci@c8000400 { + status = "okay"; + wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + bus-width = <8>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8753-whistler", + "nvidia,tegra-audio-wm8753"; + nvidia,model = "NVIDIA Tegra Whistler"; + + nvidia,audio-routing = + "Headphone Jack", "LOUT1", + "Headphone Jack", "ROUT1", + "MIC2", "Mic Jack", + "MIC2N", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&codec>; + }; +}; diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index 9e84fe4f2aaa..30bb7332e30b 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot @@ -15,7 +15,9 @@ endif # Keep dtb files sorted alphabetically for each SoC # sam9260 +dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb +dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb # sam9263 diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 45d52567ced7..006dae8dfe44 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c @@ -14,6 +14,9 @@ #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> #include <mach/common.h> #include <mach/cp_intc.h> @@ -119,7 +122,7 @@ static const struct irq_domain_ops cp_intc_host_ops = { .xlate = irq_domain_xlate_onetwocell, }; -int __init __cp_intc_init(struct device_node *node) +int __init cp_intc_of_init(struct device_node *node, struct device_node *parent) { u32 num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; @@ -128,7 +131,14 @@ int __init __cp_intc_init(struct device_node *node) int i, irq_base; davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; - davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + if (node) { + davinci_intc_base = of_iomap(node, 0); + if (of_property_read_u32(node, "ti,intc-size", &num_irq)) + pr_warn("unable to get intc-size, default to %d\n", + num_irq); + } else { + davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); + } if (WARN_ON(!davinci_intc_base)) return -EINVAL; @@ -208,5 +218,5 @@ int __init __cp_intc_init(struct device_node *node) void __init cp_intc_init(void) { - __cp_intc_init(NULL); + cp_intc_of_init(NULL, NULL); } diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index 4e8190eed673..d13d8dfa2b0d 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h @@ -52,5 +52,6 @@ #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) void __init cp_intc_init(void); +int __init cp_intc_of_init(struct device_node *, struct device_node *); #endif /* __ASM_HARDWARE_CP_INTC_H */ diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db453145..26fe9de35ecb 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { .ctrlbit = (1 << 13), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 16), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 18), }, { @@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos4_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "exynos4210-spi.0", + .parent = &exynos4_clk_mdout_spi0.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "exynos4210-spi.1", + .parent = &exynos4_clk_mdout_spi1.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.2", + .devname = "exynos4210-spi.2", + .parent = &exynos4_clk_mdout_spi2.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, }; /* Clock initialization code */ @@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { &exynos4_clk_sclk_spi0, &exynos4_clk_sclk_spi1, &exynos4_clk_sclk_spi2, - + &exynos4_clk_mdout_spi0, + &exynos4_clk_mdout_spi1, + &exynos4_clk_mdout_spi2, }; static struct clk_lookup exynos4_clk_lookup[] = { @@ -1347,9 +1376,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), }; static int xtal_rate; diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336be2b4..774533c67066 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); } +static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); +} + static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); @@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_peric_ctrl, .ctrlbit = (1 << 14), }, { + .name = "spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 16), + }, { + .name = "spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 17), + }, { + .name = "spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_aclk_66.clk, + .enable = exynos5_clk_ip_peric_ctrl, + .ctrlbit = (1 << 18), + }, { .name = SYSMMU_CLOCK_NAME, .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), .enable = &exynos5_clk_ip_mfc_ctrl, @@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos5_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos5_clkset_group, + .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi0 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.0", + .parent = &exynos5_clk_mdout_spi0.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 16), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi1 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.1", + .parent = &exynos5_clk_mdout_spi1.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 20), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, +}; + +static struct clksrc_clk exynos5_clk_sclk_spi2 = { + .clk = { + .name = "sclk_spi", + .devname = "exynos4210-spi.2", + .parent = &exynos5_clk_mdout_spi2.clk, + .enable = exynos5_clksrc_mask_peric1_ctrl, + .ctrlbit = (1 << 24), + }, + .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, +}; + static struct clksrc_clk exynos5_clksrcs[] = { { .clk = { @@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { &exynos5_clk_dout_mmc4, &exynos5_clk_aclk_acp, &exynos5_clk_pclk_acp, + &exynos5_clk_sclk_spi0, + &exynos5_clk_sclk_spi1, + &exynos5_clk_sclk_spi2, + &exynos5_clk_mdout_spi0, + &exynos5_clk_mdout_spi1, + &exynos5_clk_mdout_spi2, }; static struct clk *exynos5_clk_cdev[] = { @@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), + CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk), + CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk), + CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 7a4b4789eb72..35bced6f9092 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -195,6 +195,10 @@ #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 +#define IRQ_SPI0 EXYNOS4_IRQ_SPI0 +#define IRQ_SPI1 EXYNOS4_IRQ_SPI1 +#define IRQ_SPI2 EXYNOS4_IRQ_SPI2 + #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index ca4aa89aa46b..c72b675b3e4b 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -154,6 +154,9 @@ #define EXYNOS4_PA_SPI0 0x13920000 #define EXYNOS4_PA_SPI1 0x13930000 #define EXYNOS4_PA_SPI2 0x13940000 +#define EXYNOS5_PA_SPI0 0x12D20000 +#define EXYNOS5_PA_SPI1 0x12D30000 +#define EXYNOS5_PA_SPI2 0x12D40000 #define EXYNOS4_PA_GPIO1 0x11400000 #define EXYNOS4_PA_GPIO2 0x11000000 diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e7e9743543ac..b2b5d5faa748 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { "exynos4-sdhci.3", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), "s3c2440-i2c.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), {}, diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 7b1e11a228cc..ef770bc2318f 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s3c2440-i2c.0", NULL), OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), "s3c2440-i2c.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0, + "exynos4210-spi.0", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1, + "exynos4210-spi.1", NULL), + OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, + "exynos4210-spi.2", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index 833ff40ee0e8..4999829d1c6e 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c @@ -9,21 +9,10 @@ */ #include <linux/gpio.h> -#include <linux/platform_device.h> - #include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); @@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); @@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .clk_from_cmu = true, - .tx_st_done = 25, -}; - -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 1bba37c6598b..7616101a35f0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -52,6 +52,7 @@ config SOC_IMX25 select ARCH_MX25 select COMMON_CLK select CPU_ARM926T + select HAVE_CAN_FLEXCAN if CAN select ARCH_MXC_IOMUX_V3 select MXC_AVIC @@ -79,6 +80,7 @@ config SOC_IMX35 select HAVE_EPIT select MXC_AVIC select SMP_ON_UP if SMP + select HAVE_CAN_FLEXCAN if CAN config SOC_IMX5 select CPU_V7 @@ -105,6 +107,7 @@ config SOC_IMX53 select SOC_IMX5 select ARCH_MX5 select ARCH_MX53 + select HAVE_CAN_FLEXCAN if CAN if ARCH_IMX_V4_V5 @@ -556,6 +559,14 @@ config MACH_BUG Include support for BUGBase 1.3 platform. This includes specific configurations for the board and its peripherals. +config MACH_IMX31_DT + bool "Support i.MX31 platforms from device tree" + select SOC_IMX31 + select USE_OF + help + Include support for Freescale i.MX31 based platforms + using the device tree for discovery. + comment "MX35 platforms:" config MACH_PCM043 @@ -826,10 +837,12 @@ config SOC_IMX6Q select COMMON_CLK select CPU_V7 select HAVE_ARM_SCU + select HAVE_CAN_FLEXCAN if CAN select HAVE_IMX_GPC select HAVE_IMX_MMDC select HAVE_IMX_SRC select HAVE_SMP + select MFD_ANATOP select PINCTRL select PINCTRL_IMX6Q select USE_OF diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ff29421414f2..07f7c226e4cf 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o obj-$(CONFIG_MACH_BUG) += mach-bug.o +obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o # i.MX35 based machines obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index c9a06d800f8e..f87a48fc74e1 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -20,6 +20,7 @@ #include <linux/clkdev.h> #include <linux/io.h> #include <linux/err.h> +#include <linux/of.h> #include <mach/hardware.h> #include <mach/mx31.h> @@ -179,3 +180,21 @@ int __init mx31_clocks_init(unsigned long fref) return 0; } + +#ifdef CONFIG_OF +int __init mx31_clocks_init_dt(void) +{ + struct device_node *np; + u32 fref = 26000000; /* default */ + + for_each_compatible_node(np, NULL, "fixed-clock") { + if (!of_device_is_compatible(np, "fsl,imx-osc26m")) + continue; + + if (!of_property_read_u32(np, "clock-frequency", &fref)) + break; + } + + return mx31_clocks_init(fref); +} +#endif diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index abb42e7453a9..ea89520b6e22 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -147,12 +147,12 @@ enum mx6q_clks { esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, - mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, + mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, clk_max }; @@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void) clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); + clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); + clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); + /* name parent_name reg idx */ clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); @@ -318,7 +321,7 @@ int __init mx6q_clocks_init(void) clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); /* name parent_name reg shift */ - clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4); + clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); @@ -357,6 +360,7 @@ int __init mx6q_clocks_init(void) clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); + clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); @@ -391,6 +395,18 @@ int __init mx6q_clocks_init(void) clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[twd], NULL, "smp_twd"); + clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); + clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); + clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); + clk_register_clkdev(clk[usboh3], NULL, "2184000.usb"); + clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); + clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); + clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); + clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy"); + clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy"); clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c new file mode 100644 index 000000000000..a68ba207b2b7 --- /dev/null +++ b/arch/arm/mach-imx/imx31-dt.c @@ -0,0 +1,63 @@ +/* + * Copyright 2012 Sascha Hauer, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/irq.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <mach/common.h> +#include <mach/mx31.h> + +static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = { + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR, + "imx21-uart.0", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR, + "imx21-uart.1", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR, + "imx21-uart.2", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR, + "imx21-uart.3", NULL), + OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR, + "imx21-uart.4", NULL), + { /* sentinel */ } +}; + +static void __init imx31_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, + imx31_auxdata_lookup, NULL); +} + +static void __init imx31_timer_init(void) +{ + mx31_clocks_init_dt(); +} + +static struct sys_timer imx31_timer = { + .init = imx31_timer_init, +}; + +static const char *imx31_dt_board_compat[] __initdata = { + "fsl,imx31", + NULL +}; + +DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") + .map_io = mx31_map_io, + .init_early = imx31_init_early, + .init_irq = mx31_init_irq, + .handle_irq = imx31_handle_irq, + .timer = &imx31_timer, + .init_machine = imx31_dt_init, + .dt_compat = imx31_dt_board_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index b47e98b7d539..140f55010630 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -24,6 +24,7 @@ #include <linux/pinctrl/machine.h> #include <linux/phy.h> #include <linux/micrel_phy.h> +#include <linux/mfd/anatop.h> #include <asm/smp_twd.h> #include <asm/hardware/cache-l2x0.h> #include <asm/hardware/gic.h> @@ -113,6 +114,45 @@ static void __init imx6q_sabrelite_init(void) imx6q_sabrelite_cko1_setup(); } +static void __init imx6q_usb_init(void) +{ + struct device_node *np; + struct platform_device *pdev = NULL; + struct anatop *adata = NULL; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); + if (np) + pdev = of_find_device_by_node(np); + if (pdev) + adata = platform_get_drvdata(pdev); + if (!adata) { + if (np) + of_node_put(np); + return; + } + +#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0 +#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210 + +#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000 + + /* + * The external charger detector needs to be disabled, + * or the signal at DP will be poor + */ + anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT, + BM_ANADIG_USB_CHRG_DETECT_EN_B + | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, + ~0); + anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT, + BM_ANADIG_USB_CHRG_DETECT_EN_B | + BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, + ~0); + + of_node_put(np); +} + static void __init imx6q_init_machine(void) { /* @@ -127,6 +167,7 @@ static void __init imx6q_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); imx6q_pm_init(); + imx6q_usb_init(); } static void __init imx6q_map_io(void) diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 91cf0625819c..ccdf83b17cf1 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig @@ -16,6 +16,7 @@ config SOC_IMX28 bool select ARM_AMBA select CPU_ARM926T + select HAVE_CAN_FLEXCAN if CAN select HAVE_PWM select PINCTRL_IMX28 diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 07b11fe6453f..4582999cf080 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot @@ -1 +1,10 @@ zreladdr-y += 0x40008000 + +dtb-y += imx23-evk.dtb \ + imx23-olinuxino.dtb \ + imx23-stmp378x_devb.dtb \ + imx28-apx4devkit.dtb \ + imx28-cfa10036.dtb \ + imx28-evk.dtb \ + imx28-m28evk.dtb \ + imx28-tx28.dtb \ diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 9acdd6387047..9ee5cede3d42 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h @@ -10,7 +10,7 @@ */ #include <mach/mx23.h> #include <mach/devices-common.h> -#include <mach/mxsfb.h> +#include <linux/mxsfb.h> #include <linux/amba/bus.h> static inline int mx23_add_duart(void) diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 84b2960df117..fcab431060f4 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h @@ -10,7 +10,7 @@ */ #include <mach/mx28.h> #include <mach/devices-common.h> -#include <mach/mxsfb.h> +#include <linux/mxsfb.h> #include <linux/amba/bus.h> static inline int mx28_add_duart(void) diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c index 5a75b7180f74..76b53f73418e 100644 --- a/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c @@ -10,7 +10,7 @@ #include <mach/mx23.h> #include <mach/mx28.h> #include <mach/devices-common.h> -#include <mach/mxsfb.h> +#include <linux/mxsfb.h> #ifdef CONFIG_SOC_IMX23 struct platform_device *__init mx23_add_mxsfb( diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h deleted file mode 100644 index e4d79791515e..000000000000 --- a/arch/arm/mach-mxs/include/mach/mxsfb.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_FB_H -#define __MACH_FB_H - -#include <linux/fb.h> - -#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ -#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ -#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ -#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ - -#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) -#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */ - -struct mxsfb_platform_data { - struct fb_videomode *mode_list; - unsigned mode_count; - - unsigned default_bpp; - - unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ - unsigned ld_intf_width; /* refer STMLCDIF_* macros */ - - unsigned fb_size; /* Size of the video memory. If zero a - * default will be used - */ - unsigned long fb_phys; /* physical address for the video memory. If - * zero the framebuffer memory will be dynamically - * allocated. If specified,fb_size must also be specified. - * fb_phys must be unused by Linux. - */ -}; - -#endif /* __MACH_FB_H */ diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8cac94b33020..648bdd05d38b 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -16,12 +16,95 @@ #include <linux/init.h> #include <linux/init.h> #include <linux/irqdomain.h> +#include <linux/micrel_phy.h> +#include <linux/mxsfb.h> #include <linux/of_irq.h> #include <linux/of_platform.h> +#include <linux/phy.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/common.h> +static struct fb_videomode mx23evk_video_modes[] = { + { + .name = "Samsung-LMS430HF02", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 108096, /* picosecond (9.2 MHz) */ + .left_margin = 15, + .right_margin = 8, + .upper_margin = 12, + .lower_margin = 4, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static struct fb_videomode mx28evk_video_modes[] = { + { + .name = "Seiko-43WVF1G", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 29851, /* picosecond (33.5 MHz) */ + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static struct fb_videomode m28evk_video_modes[] = { + { + .name = "Ampire AM-800480R2TMQW-T01H", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30066, /* picosecond (33.26 MHz) */ + .left_margin = 0, + .right_margin = 256, + .upper_margin = 0, + .lower_margin = 45, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, + }, +}; + +static struct fb_videomode apx4devkit_video_modes[] = { + { + .name = "HannStar PJ70112A", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33333, /* picosecond (30.00 MHz) */ + .left_margin = 88, + .right_margin = 40, + .upper_margin = 32, + .lower_margin = 13, + .hsync_len = 48, + .vsync_len = 3, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_DATA_ENABLE_HIGH_ACT | + FB_SYNC_DOTCLK_FAILING_ACT, + }, +}; + +static struct mxsfb_platform_data mxsfb_pdata __initdata; + +static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { + OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), + OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), + { /* sentinel */ } +}; + static int __init mxs_icoll_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { @@ -71,33 +154,155 @@ static struct sys_timer imx28_timer = { .init = imx28_timer_init, }; -static void __init imx28_evk_init(void) +enum mac_oui { + OUI_FSL, + OUI_DENX, +}; + +static void __init update_fec_mac_prop(enum mac_oui oui) +{ + struct device_node *np, *from = NULL; + struct property *oldmac, *newmac; + const u32 *ocotp = mxs_get_ocotp(); + u8 *macaddr; + u32 val; + int i; + + for (i = 0; i < 2; i++) { + np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); + if (!np) + return; + from = np; + + newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); + if (!newmac) + return; + newmac->value = newmac + 1; + newmac->length = 6; + + newmac->name = kstrdup("local-mac-address", GFP_KERNEL); + if (!newmac->name) { + kfree(newmac); + return; + } + + /* + * OCOTP only stores the last 4 octets for each mac address, + * so hard-code OUI here. + */ + macaddr = newmac->value; + switch (oui) { + case OUI_FSL: + macaddr[0] = 0x00; + macaddr[1] = 0x04; + macaddr[2] = 0x9f; + break; + case OUI_DENX: + macaddr[0] = 0xc0; + macaddr[1] = 0xe5; + macaddr[2] = 0x4e; + break; + } + val = ocotp[i]; + macaddr[3] = (val >> 16) & 0xff; + macaddr[4] = (val >> 8) & 0xff; + macaddr[5] = (val >> 0) & 0xff; + + oldmac = of_find_property(np, newmac->name, NULL); + if (oldmac) + prom_update_property(np, newmac, oldmac); + else + prom_add_property(np, newmac); + } +} + +static void __init imx23_evk_init(void) +{ + mxsfb_pdata.mode_list = mx23evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; +} + +static inline void enable_clk_enet_out(void) { - struct clk *clk; + struct clk *clk = clk_get_sys("enet_out", NULL); - /* Enable fec phy clock */ - clk = clk_get_sys("enet_out", NULL); if (!IS_ERR(clk)) clk_prepare_enable(clk); } +static void __init imx28_evk_init(void) +{ + enable_clk_enet_out(); + update_fec_mac_prop(OUI_FSL); + + mxsfb_pdata.mode_list = mx28evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; +} + +static void __init m28evk_init(void) +{ + enable_clk_enet_out(); + update_fec_mac_prop(OUI_DENX); + + mxsfb_pdata.mode_list = m28evk_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); + mxsfb_pdata.default_bpp = 16; + mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; +} + +static int apx4devkit_phy_fixup(struct phy_device *phy) +{ + phy->dev_flags |= MICREL_PHY_50MHZ_CLK; + return 0; +} + +static void __init apx4devkit_init(void) +{ + enable_clk_enet_out(); + + if (IS_BUILTIN(CONFIG_PHYLIB)) + phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, + apx4devkit_phy_fixup); + + mxsfb_pdata.mode_list = apx4devkit_video_modes; + mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); + mxsfb_pdata.default_bpp = 32; + mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; +} + static void __init mxs_machine_init(void) { if (of_machine_is_compatible("fsl,imx28-evk")) imx28_evk_init(); + else if (of_machine_is_compatible("fsl,imx23-evk")) + imx23_evk_init(); + else if (of_machine_is_compatible("denx,m28evk")) + m28evk_init(); + else if (of_machine_is_compatible("bluegiga,apx4devkit")) + apx4devkit_init(); of_platform_populate(NULL, of_default_bus_match_table, - NULL, NULL); + mxs_auxdata_lookup, NULL); } static const char *imx23_dt_compat[] __initdata = { "fsl,imx23-evk", + "fsl,stmp378x_devb" + "olimex,imx23-olinuxino", "fsl,imx23", NULL, }; static const char *imx28_dt_compat[] __initdata = { + "bluegiga,apx4devkit", + "crystalfontz,cfa10036", + "denx,m28evk", "fsl,imx28-evk", + "karo,tx28", "fsl,imx28", NULL, }; diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 7b4b9327e543..527c0046064d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -772,7 +772,7 @@ static int __init omap_init_wdt(void) char *oh_name = "wd_timer2"; char *dev_name = "omap_wdt"; - if (!cpu_class_is_omap2()) + if (!cpu_class_is_omap2() || of_have_populated_dt()) return 0; oh = omap_hwmod_lookup(oh_name); diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c index 8702ecfaab30..14a81c2317a4 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c @@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk), + /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */ + CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk), }; void __init s3c2416_init_clocks(int xtal) diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c index a4c5a520d994..7f689ce1be61 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c @@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = { static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk), + CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), }; void __init s3c2443_init_clocks(int xtal) diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c index aeeb2be283fa..aeb4a24ff3ed 100644 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/arch/arm/mach-s3c24xx/common-s3c2443.c @@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = { static struct clk hsspi_clk = { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s3c2443-spi.0", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_HSSPI, @@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk), + CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk), }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c index 5712c85f39b1..3d47e023ce94 100644 --- a/arch/arm/mach-s3c24xx/setup-spi.c +++ b/arch/arm/mach-s3c24xx/setup-spi.c @@ -13,20 +13,12 @@ #include <linux/platform_device.h> #include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> #include <mach/hardware.h> #include <mach/regs-gpio.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, - .high_speed = 1, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) +int s3c64xx_spi0_cfg_gpio(void) { /* enable hsspi bit in misccr */ s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 52f079a691cb..28041e83dc82 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s3c6410-spi.0", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI0, }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s3c6410-spi.1", .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, @@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = { static struct clk clk_48m_spi0 = { .name = "spi_48m", - .devname = "s3c64xx-spi.0", + .devname = "s3c6410-spi.0", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, @@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = { static struct clk clk_48m_spi1 = { .name = "spi_48m", - .devname = "s3c64xx-spi.1", + .devname = "s3c6410-spi.1", .parent = &clk_48m, .enable = s3c64xx_sclk_ctrl, .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, @@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "spi-bus", - .devname = "s3c64xx-spi.0", + .devname = "s3c6410-spi.0", .ctrlbit = S3C_CLKCON_SCLK_SPI0, .enable = s3c64xx_sclk_ctrl, }, @@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "spi-bus", - .devname = "s3c64xx-spi.1", + .devname = "s3c6410-spi.1", .ctrlbit = S3C_CLKCON_SCLK_SPI1, .enable = s3c64xx_sclk_ctrl, }, @@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), + CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0), + CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1), }; #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index fe1a98cf0e4c..57b1ff4b2d7c 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h @@ -21,6 +21,7 @@ */ enum dma_ch { /* DMA0/SDMA0 */ + DMACH_DT_PROP = -1, /* not yet supported, do not use */ DMACH_UART0 = 0, DMACH_UART0_SRC2, DMACH_UART1, diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index d0c352d861f8..6dd4fae33a82 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -799,7 +799,7 @@ static void __init crag6410_machine_init(void) i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); samsung_keypad_set_platdata(&crag6410_keypad_data); - s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1); + s3c64xx_spi0_set_platdata(NULL, 0, 1); platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c index d9592ad7a825..4dc53450d715 100644 --- a/arch/arm/mach-s3c64xx/setup-spi.c +++ b/arch/arm/mach-s3c64xx/setup-spi.c @@ -9,19 +9,10 @@ */ #include <linux/gpio.h> -#include <linux/platform_device.h> - #include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -30,13 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .tx_st_done = 21, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index ee1e8e7f5631..000445596ec4 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 21), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 22), @@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .ctrlbit = (1 << 20), .enable = s5p64x0_sclk_ctrl, }, @@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .ctrlbit = (1 << 21), .enable = s5p64x0_sclk_ctrl, }, @@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index dae6a13f43bb..f3e0ef3d27c9 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 17), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 21), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .parent = &clk_pclk_low.clk, .enable = s5p64x0_pclk_ctrl, .ctrlbit = (1 << 22), @@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5p64x0-spi.0", .ctrlbit = (1 << 20), .enable = s5p64x0_sclk_ctrl, }, @@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5p64x0-spi.1", .ctrlbit = (1 << 21), .enable = s5p64x0_sclk_ctrl, }, @@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c index e9b841240352..7664356720ca 100644 --- a/arch/arm/mach-s5p64x0/setup-spi.c +++ b/arch/arm/mach-s5p64x0/setup-spi.c @@ -9,21 +9,10 @@ */ #include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/io.h> - #include <plat/gpio-cfg.h> -#include <plat/cpu.h> -#include <plat/s3c64xx-spi.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { if (soc_is_s5p6450()) s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, @@ -36,13 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .tx_st_done = 25, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { if (soc_is_s5p6450()) s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 16eca4ea2010..926219791f0d 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 5), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pc100-spi.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 6), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pc100-spi.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 7), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "s5pc100-spi.2", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_4_ctrl, .ctrlbit = (1 << 8), @@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = { static struct clk clk_48m_spi0 = { .name = "spi_48m", - .devname = "s3c64xx-spi.0", + .devname = "s5pc100-spi.0", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 7), @@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = { static struct clk clk_48m_spi1 = { .name = "spi_48m", - .devname = "s3c64xx-spi.1", + .devname = "s5pc100-spi.1", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 8), @@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = { static struct clk clk_48m_spi2 = { .name = "spi_48m", - .devname = "s3c64xx-spi.2", + .devname = "s5pc100-spi.2", .parent = &clk_mout_48m.clk, .enable = s5pc100_sclk0_ctrl, .ctrlbit = (1 << 9), @@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pc100-spi.0", .ctrlbit = (1 << 4), .enable = s5pc100_sclk0_ctrl, }, @@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pc100-spi.1", .ctrlbit = (1 << 5), .enable = s5pc100_sclk0_ctrl, }, @@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = { static struct clksrc_clk clk_sclk_spi2 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.2", + .devname = "s5pc100-spi.2", .ctrlbit = (1 << 6), .enable = s5pc100_sclk0_ctrl, }, @@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), - CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), + CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0), + CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1), + CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2), + CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), }; void __init s5pc100_register_clocks(void) diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c index 431a6f747caa..183567961de1 100644 --- a/arch/arm/mach-s5pc100/setup-spi.c +++ b/arch/arm/mach-s5pc100/setup-spi.c @@ -9,20 +9,10 @@ */ #include <linux/gpio.h> -#include <linux/platform_device.h> - #include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -31,14 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); @@ -47,14 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI2 -struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 13, - .high_speed = 1, - .tx_st_done = 21, -}; - -int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi2_cfg_gpio(void) { s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 09609d50961d..fcdf52dbcc49 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 11), }, { .name = "spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pv210-spi.0", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<12), }, { .name = "spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pv210-spi.1", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<13), }, { .name = "spi", - .devname = "s3c64xx-spi.2", + .devname = "s5pv210-spi.2", .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<14), @@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = { static struct clksrc_clk clk_sclk_spi0 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.0", + .devname = "s5pv210-spi.0", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 16), }, @@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = { static struct clksrc_clk clk_sclk_spi1 = { .clk = { .name = "sclk_spi", - .devname = "s3c64xx-spi.1", + .devname = "s5pv210-spi.1", .enable = s5pv210_clk_mask0_ctrl, .ctrlbit = (1 << 17), }, @@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), - CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), - CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), + CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), + CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), }; void __init s5pv210_register_clocks(void) diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c index f43c5048a37d..81aecc162f82 100644 --- a/arch/arm/mach-s5pv210/setup-spi.c +++ b/arch/arm/mach-s5pv210/setup-spi.c @@ -9,20 +9,10 @@ */ #include <linux/gpio.h> -#include <linux/platform_device.h> - #include <plat/gpio-cfg.h> -#include <plat/s3c64xx-spi.h> #ifdef CONFIG_S3C64XX_DEV_SPI0 -struct s3c64xx_spi_info s3c64xx_spi0_pdata = { - .fifo_lvl_mask = 0x1ff, - .rx_lvl_offset = 15, - .high_speed = 1, - .tx_st_done = 25, -}; - -int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi0_cfg_gpio(void) { s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); @@ -33,14 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) #endif #ifdef CONFIG_S3C64XX_DEV_SPI1 -struct s3c64xx_spi_info s3c64xx_spi1_pdata = { - .fifo_lvl_mask = 0x7f, - .rx_lvl_offset = 15, - .high_speed = 1, - .tx_st_done = 25, -}; - -int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) +int s3c64xx_spi1_cfg_gpio(void) { s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 8040345bd971..435f00ca3c58 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -7,4 +7,5 @@ dtb-$(CONFIG_MACH_PAZ00) += tegra20-paz00.dtb dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 53d3d46dec12..c013bbf79cac 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -41,6 +41,7 @@ config MACH_HREFV60 config MACH_SNOWBALL bool "U8500 Snowball platform" select MACH_MOP500 + select LEDS_GPIO help Include support for the snowball development platform. diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 920251cf834c..18ff781cfbe4 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -80,7 +80,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { }; #endif -static struct mmci_platform_data mop500_sdi0_data = { +struct mmci_platform_data mop500_sdi0_data = { .ios_handler = mop500_sdi0_ios_handler, .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, @@ -227,7 +227,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { }; #endif -static struct mmci_platform_data mop500_sdi4_data = { +struct mmci_platform_data mop500_sdi4_data = { .ocr_mask = MMC_VDD_29_30, .f_max = 50000000, .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 4fd93f5c49ec..84461fa2a3ba 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -58,7 +58,7 @@ static struct gpio_led snowball_led_array[] = { { .name = "user_led", - .default_trigger = "none", + .default_trigger = "heartbeat", .gpio = 142, }, }; @@ -331,43 +331,12 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = { }, }; -#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm) \ -static struct nmk_i2c_controller u8500_i2c##id##_data = { \ - /* \ - * slave data setup time, which is \ - * 250 ns,100ns,10ns which is 14,6,2 \ - * respectively for a 48 Mhz \ - * i2c clock \ - */ \ - .slsu = _slsu, \ - /* Tx FIFO threshold */ \ - .tft = _tft, \ - /* Rx FIFO threshold */ \ - .rft = _rft, \ - /* std. mode operation */ \ - .clk_freq = clk, \ - /* Slave response timeout(ms) */\ - .timeout = t_out, \ - .sm = _sm, \ -} - -/* - * The board uses 4 i2c controllers, initialize all of - * them with slave data setup time of 250 ns, - * Tx & Rx FIFO threshold values as 8 and standard - * mode of operation - */ -U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); -U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); - static void __init mop500_i2c_init(struct device *parent) { - db8500_add_i2c0(parent, &u8500_i2c0_data); - db8500_add_i2c1(parent, &u8500_i2c1_data); - db8500_add_i2c2(parent, &u8500_i2c2_data); - db8500_add_i2c3(parent, &u8500_i2c3_data); + db8500_add_i2c0(parent, NULL); + db8500_add_i2c1(parent, NULL); + db8500_add_i2c2(parent, NULL); + db8500_add_i2c3(parent, NULL); } static struct gpio_keys_button mop500_gpio_keys[] = { @@ -776,6 +745,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), /* Requires DMA bindings. */ OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), + OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), + OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), /* Requires clock name bindings. */ OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), @@ -786,6 +757,11 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), + OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), /* Requires device name bindings. */ OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), {}, @@ -820,8 +796,6 @@ static void __init u8500_init_machine(void) for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) mop500_platform_devs[i]->dev.parent = parent; - for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) - snowball_platform_devs[i]->dev.parent = parent; /* automatically probe child nodes of db8500 device */ of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); @@ -840,18 +814,6 @@ static void __init u8500_init_machine(void) mop500_uib_init(); - } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { - /* - * Devices to be DT:ed: - * snowball_led_dev = todo - * snowball_key_dev = todo - * snowball_sbnet_dev = done - * ab8500_device = done - */ - platform_add_devices(snowball_of_platform_devs, - ARRAY_SIZE(snowball_of_platform_devs)); - - snowball_sdi_init(parent); } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { /* * The HREFv60 board removed a GPIO expander and routed @@ -873,7 +835,6 @@ static void __init u8500_init_machine(void) mop500_uib_init(); } - mop500_i2c_init(parent); /* This board has full regulator constraints */ regulator_has_full_constraints(); diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 2f87b25a908a..b5bfc1a78b1a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -9,6 +9,7 @@ /* For NOMADIK_NR_GPIO */ #include <mach/irqs.h> +#include <linux/amba/mmci.h> /* Snowball specific GPIO assignments, this board has no GPIO expander */ #define SNOWBALL_ACCEL_INT1_GPIO 163 @@ -78,6 +79,8 @@ struct device; struct i2c_board_info; +extern struct mmci_platform_data mop500_sdi0_data; +extern struct mmci_platform_data mop500_sdi4_data; extern void mop500_sdi_init(struct device *parent); extern void snowball_sdi_init(struct device *parent); diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 33275eb4c689..c8dd94f606dc 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -139,7 +139,6 @@ static struct platform_device *platform_devs[] __initdata = { static struct platform_device *of_platform_devs[] __initdata = { &u8500_dma40_device, - &db8500_pmu_device, }; static resource_size_t __initdata db8500_gpio_base[] = { @@ -237,7 +236,6 @@ struct device * __init u8500_of_init_devices(void) parent = db8500_soc_device_init(); - db8500_add_rtc(parent); db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); platform_device_register_data(parent, @@ -249,7 +247,7 @@ struct device * __init u8500_of_init_devices(void) /* * Devices to be DT:ed: * u8500_dma40_device = todo - * db8500_pmu_device = todo + * db8500_pmu_device = done * db8500_prcmu_device = done */ platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index e429ca1b814a..7cfcc44537f0 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -67,6 +67,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx27_clocks_init_dt(void); +extern int mx31_clocks_init_dt(void); extern int mx51_clocks_init_dt(void); extern int mx53_clocks_init_dt(void); extern int mx6q_clocks_init(void); diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 6303974c2ee0..74e31ce35538 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -1513,7 +1513,7 @@ static struct resource s3c64xx_spi0_resource[] = { }; struct platform_device s3c64xx_device_spi0 = { - .name = "s3c64xx-spi", + .name = "s3c6410-spi", .id = 0, .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), .resource = s3c64xx_spi0_resource, @@ -1523,13 +1523,10 @@ struct platform_device s3c64xx_device_spi0 = { }, }; -void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs) +void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs) { - if (!pd) { - pr_err("%s:Need to pass platform data\n", __func__); - return; - } + struct s3c64xx_spi_info pd; /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { @@ -1537,12 +1534,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, return; } - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - if (!pd->cfg_gpio) - pd->cfg_gpio = s3c64xx_spi0_cfg_gpio; + pd.num_cs = num_cs; + pd.src_clk_nr = src_clk_nr; + pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; - s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0); + s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0); } #endif /* CONFIG_S3C64XX_DEV_SPI0 */ @@ -1555,7 +1551,7 @@ static struct resource s3c64xx_spi1_resource[] = { }; struct platform_device s3c64xx_device_spi1 = { - .name = "s3c64xx-spi", + .name = "s3c6410-spi", .id = 1, .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), .resource = s3c64xx_spi1_resource, @@ -1565,26 +1561,20 @@ struct platform_device s3c64xx_device_spi1 = { }, }; -void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs) +void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs) { - if (!pd) { - pr_err("%s:Need to pass platform data\n", __func__); - return; - } - /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { pr_err("%s: Invalid SPI configuration\n", __func__); return; } - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - if (!pd->cfg_gpio) - pd->cfg_gpio = s3c64xx_spi1_cfg_gpio; + pd.num_cs = num_cs; + pd.src_clk_nr = src_clk_nr; + pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; - s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1); + s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); } #endif /* CONFIG_S3C64XX_DEV_SPI1 */ @@ -1597,7 +1587,7 @@ static struct resource s3c64xx_spi2_resource[] = { }; struct platform_device s3c64xx_device_spi2 = { - .name = "s3c64xx-spi", + .name = "s3c6410-spi", .id = 2, .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), .resource = s3c64xx_spi2_resource, @@ -1607,13 +1597,10 @@ struct platform_device s3c64xx_device_spi2 = { }, }; -void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs) +void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs) { - if (!pd) { - pr_err("%s:Need to pass platform data\n", __func__); - return; - } + struct s3c64xx_spi_info pd; /* Reject invalid configuration */ if (!num_cs || src_clk_nr < 0) { @@ -1621,11 +1608,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, return; } - pd->num_cs = num_cs; - pd->src_clk_nr = src_clk_nr; - if (!pd->cfg_gpio) - pd->cfg_gpio = s3c64xx_spi2_cfg_gpio; + pd.num_cs = num_cs; + pd.src_clk_nr = src_clk_nr; + pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; - s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2); + s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); } #endif /* CONFIG_S3C64XX_DEV_SPI2 */ diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index fa95e9a00972..ceba18d23a5a 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -18,7 +18,6 @@ struct platform_device; * @fb_delay: Slave specific feedback delay. * Refer to FB_CLK_SEL register definition in SPI chapter. * @line: Custom 'identity' of the CS line. - * @set_level: CS line control. * * This is per SPI-Slave Chipselect information. * Allocate and initialize one in machine init code and make the @@ -27,57 +26,41 @@ struct platform_device; struct s3c64xx_spi_csinfo { u8 fb_delay; unsigned line; - void (*set_level)(unsigned line_id, int lvl); }; /** * struct s3c64xx_spi_info - SPI Controller defining structure * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. - * @clk_from_cmu: If the SPI clock/prescalar control block is present - * by the platform's clock-management-unit and not in SPI controller. * @num_cs: Number of CS this controller emulates. * @cfg_gpio: Configure pins for this SPI controller. - * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 - * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number - * @high_speed: If the controller supports HIGH_SPEED_EN bit - * @tx_st_done: Depends on tx fifo_lvl field */ struct s3c64xx_spi_info { int src_clk_nr; - bool clk_from_cmu; - int num_cs; - - int (*cfg_gpio)(struct platform_device *pdev); - - /* Following two fields are for future compatibility */ - int fifo_lvl_mask; - int rx_lvl_offset; - int high_speed; - int tx_st_done; + int (*cfg_gpio)(void); }; /** * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board * initialization code. - * @pd: SPI platform data to set. + * @cfg_gpio: Pointer to gpio setup function. * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. * @num_cs: Number of elements in the 'cs' array. * * Call this from machine init code for each SPI Controller that * has some chips attached to it. */ -extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs); -extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs); -extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, - int src_clk_nr, int num_cs); +extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); +extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); +extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, + int num_cs); /* defined by architecture to configure gpio */ -extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); -extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); -extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); +extern int s3c64xx_spi0_cfg_gpio(void); +extern int s3c64xx_spi1_cfg_gpio(void); +extern int s3c64xx_spi2_cfg_gpio(void); extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; |