diff options
| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:20 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:15 +0000 |
| commit | 5b380ae0e2b3f354bd1274008286b10ee8585015 (patch) | |
| tree | 3fb64515c54f16a1a5303019d0882fff70135001 /arch | |
| parent | 8fe2a9c578b07c9a631fbf7cd9e278ffa6619869 (diff) | |
arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
Convert ID_MMFR4_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-22-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 10 | ||||
| -rw-r--r-- | arch/arm64/tools/sysreg | 38 |
2 files changed, 38 insertions, 10 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index be4015d22a30..b9fdb1e0a451 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -171,7 +171,6 @@ #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) #define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5) #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_MMFR5_EL1 sys_reg(3, 0, 0, 3, 6) #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) @@ -727,15 +726,6 @@ #define ID_ISAR6_EL1_DP_SHIFT 4 #define ID_ISAR6_EL1_JSCVT_SHIFT 0 -#define ID_MMFR4_EL1_EVT_SHIFT 28 -#define ID_MMFR4_EL1_CCIDX_SHIFT 24 -#define ID_MMFR4_EL1_LSM_SHIFT 20 -#define ID_MMFR4_EL1_HPDS_SHIFT 16 -#define ID_MMFR4_EL1_CnP_SHIFT 12 -#define ID_MMFR4_EL1_XNX_SHIFT 8 -#define ID_MMFR4_EL1_AC2_SHIFT 4 -#define ID_MMFR4_EL1_SpecSEI_SHIFT 0 - #define ID_MMFR5_EL1_ETS_SHIFT 0 #define ID_PFR0_EL1_DIT_SHIFT 24 diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7573312ef249..7cd258ee7a0f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -223,6 +223,44 @@ Enum 3:0 CMaintVA EndEnum EndSysreg +Sysreg ID_MMFR4_EL1 3 0 0 2 6 +Res0 63:32 +Enum 31:28 EVT + 0b0000 NI + 0b0001 NO_TLBIS + 0b0010 TLBIS +EndEnum +Enum 27:24 CCIDX + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 23:20 LSM + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 19:16 HPDS + 0b0000 NI + 0b0001 AA32HPD + 0b0010 HPDS2 +EndEnum +Enum 15:12 CnP + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 11:8 XNX + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 7:4 AC2 + 0b0000 NI + 0b0001 IMP +EndEnum +Enum 3:0 SpecSEI + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64PFR0_EL1 3 0 0 4 0 Enum 63:60 CSV3 0b0000 NI |