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| author | jianzh <Jiange.Zhao@amd.com> | 2020-02-21 14:28:12 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 00:32:23 -0500 |
| commit | e7429606bb6ad846cfa4f3dd26a328b1d3e76a54 (patch) | |
| tree | 6dfa8a60c22bdbe89fbee310d00d44ce2d50391e /drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h | |
| parent | 781345f9ef03cbdc7720897b6b2aa7dfe7ec69ac (diff) | |
drm/amdgpu/sriov: Use VF-accessible register for gpu_clock_count
Navi12 VK CTS subtest timestamp.calibrated.dev_domain_test failed
because mmRLC_CAPTURE_GPU_CLOCK_COUNT register cannot be
written in VF due to security policy.
Solution: use a VF-accessible timestamp register pair
mmGOLDEN_TSC_COUNT_LOWER/UPPER for SRIOV case.
v2: according to Deucher Alexander's advice, switch to
mmGOLDEN_TSC_COUNT_LOWER/UPPER for both bare metal and SRIOV.
Signed-off-by: jianzh <Jiange.Zhao@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h')
0 files changed, 0 insertions, 0 deletions