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| author | Rohit Khaire <rohit.khaire@amd.com> | 2021-06-04 11:02:56 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:02:44 -0400 |
| commit | 18703923a66aecf6f7ded0e16d22eb412ddae72f (patch) | |
| tree | ef6167ecd622656f0def728aa2f31636089e1c5d /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |
| parent | 810085ddb7b76c1cc5059a1feb3b1250eceacf23 (diff) | |
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c')
0 files changed, 0 insertions, 0 deletions