diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2021-10-04 15:19:10 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-04 15:23:01 -0400 |
| commit | 1d789535a03679e5ce0b56a0d32a5e44596dfcdb (patch) | |
| tree | ccc2b1827bb7efc4b939f56b49fc4bb7236d100b /drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | |
| parent | d0761fd24ea1e57ce4e4ae7e373fef7b8a2caed8 (diff) | |
drm/amdgpu: convert IP version array to include instances
Allow us to query instances versions more cleanly.
Instancing support is not consistent unfortunately. SDMA is a
good example. Sienna cichlid has 4 total SDMA instances, each
enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8
total SDMA instances, but they are enumerated as multiple
instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC
is another example. On most chips there are multiple
instances with the same HWID. This allows us to support both
forms.
v2: rebase
v3: clarify instancing support
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c index e0cb919b4814..25f8e93e5ec3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c @@ -153,7 +153,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 0, 0): case IP_VERSION(2, 0, 2): mmhub_cid = mmhub_client_ids_navi1x[cid][rw]; @@ -569,7 +569,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) return; - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 1, 0): case IP_VERSION(2, 1, 1): case IP_VERSION(2, 1, 2): @@ -603,7 +603,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); } - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 1, 0): case IP_VERSION(2, 1, 1): case IP_VERSION(2, 1, 2): @@ -629,7 +629,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) return; - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 1, 0): case IP_VERSION(2, 1, 1): case IP_VERSION(2, 1, 2): @@ -646,7 +646,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; if (def != data) { - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 1, 0): case IP_VERSION(2, 1, 1): case IP_VERSION(2, 1, 2): @@ -665,7 +665,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, if (amdgpu_sriov_vf(adev)) return 0; - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 0, 0): case IP_VERSION(2, 0, 2): case IP_VERSION(2, 1, 0): @@ -690,7 +690,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) if (amdgpu_sriov_vf(adev)) *flags = 0; - switch (adev->ip_versions[MMHUB_HWIP]) { + switch (adev->ip_versions[MMHUB_HWIP][0]) { case IP_VERSION(2, 1, 0): case IP_VERSION(2, 1, 1): case IP_VERSION(2, 1, 2): |