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| author | Dave Airlie <airlied@redhat.com> | 2018-03-21 11:46:05 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2018-03-21 11:46:05 +1000 |
| commit | 287d2ac36b6f2830ea4ef66c110abc0f47a9a658 (patch) | |
| tree | 04214f156461a95c2f7ca5a8821063cad7fc515e /drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | |
| parent | 963976cfe9c54d4d9e725e61c90c47a4af6b5ea2 (diff) | |
| parent | 6da2b9332c572fcda94de9631f8fa514f574388a (diff) | |
Merge branch 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux into drm-next
- Continued cleanup and restructuring of powerplay
- Fetch VRAM type from vbios rather than hardcoding for SOC15 asics
- Allow ttm to drop its backing store when drivers don't need it
- DC bandwidth calc updates
- Enable DC backlight control pre-DCE11 asics
- Enable DC on all supported asics
- DC Fixes for planes due to the way our hw is ordered vs what drm expects
- DC CTM/regamma fixes
- Misc cleanup and bug fixes
* 'drm-next-4.17' of git://people.freedesktop.org/~agd5f/linux: (89 commits)
amdgpu/dm: Default PRE_VEGA ASIC support to 'y'
drm/amd/pp: Remove the cgs wrapper for notify smu version on APU
drm/amd/display: fix dereferencing possible ERR_PTR()
drm/amd/display: Refine disable VGA
drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernel
drm/radeon: Don't turn off DP sink when disconnected
drm/amd/pp: Rename file name cz_* to smu8_*
drm/amd/pp: Replace function/struct name cz_* with smu8_*
drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.c
drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.c
drm/amd/pp: Remove dead header file pp_asicblocks.h
drm/amd/pp: Delete dead code on cz_clockpowergating.c
drm/amdgpu: Call amdgpu_ucode_fini_bo in amd_powerplay.c
drm/amdgpu: Remove wrapper layer of smu ip functions
drm/amdgpu: Don't compared ip_block_type with ip_block_index
drm/amdgpu: Plus NULL function pointer check
drm/amd/pp: Move helper functions to smu_help.c
drm/amd/pp: Replace rv_* with smu10_*
drm/amd/pp: Fix function parameter not correct
drm/amd/pp: Add rv_copy_table_from/to_smc to smu backend function table
...
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h index 67e78576a9eb..b4a9ceea334b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h @@ -24,7 +24,9 @@ #ifndef __MXGPU_AI_H__ #define __MXGPU_AI_H__ -#define AI_MAILBOX_TIMEDOUT 12000 +#define AI_MAILBOX_POLL_ACK_TIMEDOUT 500 +#define AI_MAILBOX_POLL_MSG_TIMEDOUT 12000 +#define AI_MAILBOX_POLL_FLR_TIMEDOUT 500 enum idh_request { IDH_REQ_GPU_INIT_ACCESS = 1, @@ -51,4 +53,7 @@ int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev); int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev); void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev); +#define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 +#define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1 + #endif |