diff options
| author | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2023-11-10 15:40:12 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2023-11-14 15:05:22 +0530 |
| commit | 87c8812f4b009b5a5d38b1560b45d4a1cc4b24c5 (patch) | |
| tree | 398412a10a73ed544b4605aa267baf50315c6405 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | 59a266f068b4f9f54c58e4066ac9ee9023ad9232 (diff) | |
drm/i915/display: Consider fractional vdsc bpp while computing m_n values
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).' (Sui Jingfeng).
v2:
Rebase and pass bits_per_pixel in U6.4 format.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-4-ankit.k.nautiyal@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4db902dc6eb1..0cb9405f59ea 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -71,7 +71,7 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, - bool ssc, bool dsc, int bpp) + bool ssc, bool dsc, int bpp_x16) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -95,7 +95,7 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, overhead = drm_dp_bw_overhead(crtc_state->lane_count, adjusted_mode->hdisplay, dsc_slice_count, - to_bpp_x16(bpp), + bpp_x16, flags); /* @@ -108,16 +108,16 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, const struct intel_connector *connector, bool ssc, bool dsc, - int bpp, + int bpp_x16, struct intel_link_m_n *m_n) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int overhead = intel_dp_mst_bw_overhead(crtc_state, connector, - ssc, dsc, bpp); + ssc, dsc, bpp_x16); - intel_link_compute_m_n(bpp, crtc_state->lane_count, + intel_link_compute_m_n(bpp_x16, crtc_state->lane_count, adjusted_mode->crtc_clock, crtc_state->port_clock, overhead, @@ -181,9 +181,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, link_bpp = dsc ? bpp : intel_dp_output_bpp(crtc_state->output_format, bpp); - intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp, + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, to_bpp_x16(link_bpp), &crtc_state->dp_m_n); - intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp, + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, to_bpp_x16(link_bpp), &remote_m_n); /* |