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| author | Thomas Zimmermann <tzimmermann@suse.de> | 2022-11-05 16:02:42 +0100 |
|---|---|---|
| committer | Thomas Zimmermann <tzimmermann@suse.de> | 2022-11-05 16:08:36 +0100 |
| commit | 8e4e4c2f53ffcb0ef746dc3b87ce1a57c5c94c7d (patch) | |
| tree | a61fbc998223d50f8b8691b9b9ced38c21072b10 /drivers/gpu/drm/i915/gt/intel_gtt.h | |
| parent | a8300c46385e357079248302722d2f6b48adcba1 (diff) | |
| parent | 60ba8c5bd94e17ab4b024f5cecf8b48e2cf36412 (diff) | |
Merge drm/drm-next into drm-misc-next
Backmerging drm/drm-next to get the latest changes in the xlnx driver.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gtt.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gtt.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index c0ca53cba9f0..4d75ba4bb41d 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -93,6 +93,7 @@ typedef u64 gen8_pte_t; #define GEN12_GGTT_PTE_LM BIT_ULL(1) #define GEN12_PDE_64K BIT(6) +#define GEN12_PTE_PS64 BIT(8) /* * Cacheability Control is a 4-bit value. The low three bits are stored in bits @@ -667,7 +668,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm, void gtt_write_workarounds(struct intel_gt *gt); -void setup_private_pat(struct intel_uncore *uncore); +void setup_private_pat(struct intel_gt *gt); int i915_vm_alloc_pt_stash(struct i915_address_space *vm, struct i915_vm_pt_stash *stash, |