diff options
author | Dave Airlie <airlied@redhat.com> | 2020-07-03 11:29:00 +1000 |
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committer | Dave Airlie <airlied@redhat.com> | 2020-07-03 11:29:01 +1000 |
commit | 1cc4af412f40bfe33f4b7e2b014a8d4b140bd8d3 (patch) | |
tree | d96fedf7190309ade03be50bc76f2afe184b386d /drivers/gpu/drm/i915/i915_request.c | |
parent | 9555152beb1143c85c03f9b9de59863cbbe89f4b (diff) | |
parent | d524b87f77364db096855d7eb714ffacec974ddf (diff) |
Merge tag 'drm-intel-next-2020-07-02' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 features for v5.9
Highlights:
- Rocket Lake (RKL) platform enabling (Matt Roper, Lucas, José, Aditya)
Gem/GT:
- Numerous selftest fixes and improvements (Chris)
- TGL, RKL, EHL workaround updates (Matts Atwood and Roper, Clint, Swathi Dhanavanthri, Chris)
- Retry faulthandlers on ENOSPC to avoid oomkiller (Chris)
- Numerous refactorings and cleanups (Chris)
- Several GT fixes around init/suspend/resume/shutdown (Chris)
- Whitelist CTX_TIMESTAMP register on non-RCS (Chris)
- Track if an engine requires forcewake w/a (Chris)
- Locking improvements (Chris)
- Timeslicing improvements (Chris)
- Add a safety submission flush in the heartbeat (Chris)
- Flush gen3 relocs harder (Chris)
- Discard a misplaced GGTT vma (Chris)
- Reduce relocation paths to async GPU relocations only (Chris)
- It's all build up with no pay off (Chris' own words...)
Display:
- A plethora of DP MST fixes (Imre)
- Implement proper dbuf global state (Ville)
- Consider dbuf bandwidth when calculating CDCLK (Stan)
- FBC fixes and refactoring (Ville)
- PSR fixes and improvements (José, Gwan-gyeong)
- Cursor size fixes (Ville)
- Overlay color and gamma fixes (Ville)
- Fix and improve FSB and HRAWCLK read out (Ville)
- Pre allocate and late cleanup of DSB cmd buffer (Animesh)
- Stop using mode->private_flags (Ville)
- Add plane color encoding support for YCBCR_BT2020 (Kishore Kadiyala)
- Update TGL Type-C DP and DKL HBR and HBR+ vswing tables (José)
- Fix DSI connector init error path (Vivek)
- A plethora of DP vswing/preemph fixes and refactoring (Ville)
- Fix TGL DKL vswing sequence selection (Vandita)
- Fix ICL hotplug interrupt disabling after storm detection (Imre)
- Retry HDCP link integrity check on failure (Oliver Barta)
- Fix TBT DPLL fractional divider (Imre)
- Fix ICL+ HBR3 source rate (Matt Atwood)
- Fix gen2 spurious underruns (Ville)
- Fix potential NULL dereference, some spelling fixes (Colin Ian King)
- Fix NULL dereference on encoder state probe (Chris)
Other:
- Backmerge to get mmap locking API (Jani)
- Distinguish Comet Lake from Coffee Lake (Chris)
- Various compiler warning fixes (Arnd Bergmann, Nathan Chancellor)
- WARN* conversions to drm_WARN* (Pankaj)
- Switch to device specific parameters with debugfs access (Jani)
- Fix agp/intel error path leak (Qiushi Wu)
- Forcewake power optimization (Chris)
- Irq handler optimization (Chris)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87wo3lkbxt.fsf@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_request.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_request.c | 40 |
1 files changed, 23 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index def62100e666..3bb7320249ae 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -42,7 +42,6 @@ #include "intel_pm.h" struct execute_cb { - struct list_head link; struct irq_work work; struct i915_sw_fence *fence; void (*hook)(struct i915_request *rq, struct dma_fence *signal); @@ -57,7 +56,7 @@ static struct i915_global_request { static const char *i915_fence_get_driver_name(struct dma_fence *fence) { - return dev_name(to_request(fence)->i915->drm.dev); + return dev_name(to_request(fence)->engine->i915->drm.dev); } static const char *i915_fence_get_timeline_name(struct dma_fence *fence) @@ -189,14 +188,15 @@ static void irq_execute_cb_hook(struct irq_work *wrk) static void __notify_execute_cb(struct i915_request *rq) { - struct execute_cb *cb; + struct execute_cb *cb, *cn; lockdep_assert_held(&rq->lock); - if (list_empty(&rq->execute_cb)) + GEM_BUG_ON(!i915_request_is_active(rq)); + if (llist_empty(&rq->execute_cb)) return; - list_for_each_entry(cb, &rq->execute_cb, link) + llist_for_each_entry_safe(cb, cn, rq->execute_cb.first, work.llnode) irq_work_queue(&cb->work); /* @@ -209,7 +209,7 @@ static void __notify_execute_cb(struct i915_request *rq) * preempt-to-idle cycle on the target engine, all the while the * master execute_cb may refire. */ - INIT_LIST_HEAD(&rq->execute_cb); + init_llist_head(&rq->execute_cb); } static inline void @@ -327,7 +327,7 @@ bool i915_request_retire(struct i915_request *rq) set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags); __notify_execute_cb(rq); } - GEM_BUG_ON(!list_empty(&rq->execute_cb)); + GEM_BUG_ON(!llist_empty(&rq->execute_cb)); spin_unlock_irq(&rq->lock); remove_from_client(rq); @@ -357,6 +357,12 @@ void i915_request_retire_upto(struct i915_request *rq) } while (i915_request_retire(tmp) && tmp != rq); } +static void __llist_add(struct llist_node *node, struct llist_head *head) +{ + node->next = head->first; + head->first = node; +} + static struct i915_request * const * __engine_active(struct intel_engine_cs *engine) { @@ -442,7 +448,7 @@ __await_execution(struct i915_request *rq, i915_sw_fence_complete(cb->fence); kmem_cache_free(global.slab_execute_cbs, cb); } else { - list_add_tail(&cb->link, &signal->execute_cb); + __llist_add(&cb->work.llnode, &signal->execute_cb); } spin_unlock_irq(&signal->lock); @@ -560,15 +566,15 @@ xfer: /* We may be recursing from the signal callback of another i915 fence */ if (!test_and_set_bit(I915_FENCE_FLAG_ACTIVE, &request->fence.flags)) { list_move_tail(&request->sched.link, &engine->active.requests); clear_bit(I915_FENCE_FLAG_PQUEUE, &request->fence.flags); + __notify_execute_cb(request); } + GEM_BUG_ON(!llist_empty(&request->execute_cb)); if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags) && !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &request->fence.flags) && !i915_request_enable_breadcrumb(request)) intel_engine_signal_breadcrumbs(engine); - __notify_execute_cb(request); - spin_unlock(&request->lock); return result; @@ -751,7 +757,7 @@ static void __i915_request_ctor(void *arg) rq->file_priv = NULL; rq->capture_list = NULL; - INIT_LIST_HEAD(&rq->execute_cb); + init_llist_head(&rq->execute_cb); } struct i915_request * @@ -806,7 +812,6 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) } } - rq->i915 = ce->engine->i915; rq->context = ce; rq->engine = ce->engine; rq->ring = ce->ring; @@ -841,7 +846,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp) rq->batch = NULL; GEM_BUG_ON(rq->file_priv); GEM_BUG_ON(rq->capture_list); - GEM_BUG_ON(!list_empty(&rq->execute_cb)); + GEM_BUG_ON(!llist_empty(&rq->execute_cb)); /* * Reserve space in the ring buffer for all the commands required to @@ -1005,12 +1010,12 @@ __emit_semaphore_wait(struct i915_request *to, struct i915_request *from, u32 seqno) { - const int has_token = INTEL_GEN(to->i915) >= 12; + const int has_token = INTEL_GEN(to->engine->i915) >= 12; u32 hwsp_offset; int len, err; u32 *cs; - GEM_BUG_ON(INTEL_GEN(to->i915) < 8); + GEM_BUG_ON(INTEL_GEN(to->engine->i915) < 8); GEM_BUG_ON(i915_request_has_initial_breadcrumb(to)); /* We need to pin the signaler's HWSP until we are finished reading. */ @@ -1205,7 +1210,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence) { mark_external(rq); return i915_sw_fence_await_dma_fence(&rq->submit, fence, - i915_fence_context_timeout(rq->i915, + i915_fence_context_timeout(rq->engine->i915, fence->context), I915_FENCE_GFP); } @@ -1776,7 +1781,8 @@ long i915_request_wait(struct i915_request *rq, * (bad for battery). */ if (flags & I915_WAIT_PRIORITY) { - if (!i915_request_started(rq) && INTEL_GEN(rq->i915) >= 6) + if (!i915_request_started(rq) && + INTEL_GEN(rq->engine->i915) >= 6) intel_rps_boost(rq); } |