diff options
| author | Wenjing Liu <wenjing.liu@amd.com> | 2021-06-14 18:31:21 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-28 14:26:17 -0400 |
| commit | 5354b2bd28082032644a644448ce6fa3fb476cbe (patch) | |
| tree | 10525ebe5598790de991aae2db91964b582c9c3d /drivers/gpu | |
| parent | ed0ffb5dcde95a13bd0208db0b65416e8406699a (diff) | |
drm/amd/display: adopt DP2.0 LT SCR revision 8
[how]
revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment
in one 5 byte write aux transaction.
It specifies to read aux rd interval value as soon as we turn on TPS1
pattern.
Cc: Wayne Lin <wayne.lin@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 3313f2af139f..75735c520332 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2080,7 +2080,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( struct dc_link *link, struct link_training_settings *lt_settings) { - uint8_t loop_count = 0; + uint8_t loop_count; uint32_t aux_rd_interval = 0; uint32_t wait_time = 0; struct link_training_settings req_settings; @@ -2088,25 +2088,29 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0}; enum link_training_result status = LINK_TRAINING_SUCCESS; - /* Transmit 128b/132b_TPS1 over Main-Link and Set TRAINING_PATTERN_SET to 01h */ + /* Transmit 128b/132b_TPS1 over Main-Link */ dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, DPRX); + /* Set TRAINING_PATTERN_SET to 01h */ dpcd_set_training_pattern(link, lt_settings->pattern_for_cr); - /* Adjust TX_FFE_PRESET_VALUE as requested */ + /* Adjust TX_FFE_PRESET_VALUE and Transmit 128b/132b_TPS2 over Main-Link */ + dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval); dp_get_lane_status_and_drive_settings(link, lt_settings, dpcd_lane_status, &dpcd_lane_status_updated, &req_settings, DPRX); dp_update_drive_settings(lt_settings, req_settings); - dpcd_128b_132b_get_aux_rd_interval(link, &aux_rd_interval); dp_set_hw_lane_settings(link, lt_settings, DPRX); - dpcd_set_lane_settings(link, lt_settings, DPRX); - /* Transmit 128b/132b_TPS2 over Main-Link and Set TRAINING_PATTERN_SET to 02h */ dp_set_hw_training_pattern(link, lt_settings->pattern_for_eq, DPRX); - dpcd_set_training_pattern(link, lt_settings->pattern_for_eq); + + /* Set loop counter to start from 1 */ + loop_count = 1; + + /* Set TRAINING_PATTERN_SET to 02h and TX_FFE_PRESET_VALUE in one AUX transaction */ + dpcd_set_lt_pattern_and_lane_settings(link, lt_settings, + lt_settings->pattern_for_eq, DPRX); /* poll for channel EQ done */ while (status == LINK_TRAINING_SUCCESS) { - loop_count++; dp_wait_for_training_aux_rd_interval(link, aux_rd_interval); wait_time += aux_rd_interval; dp_get_lane_status_and_drive_settings(link, lt_settings, dpcd_lane_status, @@ -2125,6 +2129,7 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence( dp_set_hw_lane_settings(link, lt_settings, DPRX); dpcd_set_lane_settings(link, lt_settings, DPRX); } + loop_count++; } /* poll for EQ interlane align done */ |