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authorJonathan Cameron <Jonathan.Cameron@huawei.com>2022-05-08 18:56:30 +0100
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2022-06-14 11:53:16 +0100
commitd0c167ceff2d833ee493dd58164dc87bd36e48aa (patch)
tree4c600a67fbc1f6025bcd68cb8d2ee237c662d3f2 /drivers/iio/dac
parent444e38927d9af093de7cdc6afbb7afdc3485da2d (diff)
iio: dac: ad5755: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Update the comment to include 'may'. Fixes: c499d029d805 ("iio:dac: Add ad5755 driver") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-51-jic23@kernel.org
Diffstat (limited to 'drivers/iio/dac')
-rw-r--r--drivers/iio/dac/ad5755.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/iio/dac/ad5755.c b/drivers/iio/dac/ad5755.c
index 1a63b8456725..beadfa938d2d 100644
--- a/drivers/iio/dac/ad5755.c
+++ b/drivers/iio/dac/ad5755.c
@@ -189,14 +189,14 @@ struct ad5755_state {
struct mutex lock;
/*
- * DMA (thus cache coherency maintenance) requires the
+ * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
union {
__be32 d32;
u8 d8[4];
- } data[2] ____cacheline_aligned;
+ } data[2] __aligned(IIO_DMA_MINALIGN);
};
enum ad5755_type {