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author | Weiyi Lu <weiyi.lu@mediatek.com> | 2019-08-28 17:11:36 +0800 |
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committer | Matthias Brugger <matthias.bgg@gmail.com> | 2019-11-07 10:11:04 +0100 |
commit | 90a943145e2ef17b559ef9e98a7c12a1abc9ae84 (patch) | |
tree | 14da1d1d53402ea498bd1a71d74c2f69e6872d4e /drivers/soc/mediatek/mtk-scpsys.c | |
parent | 54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff) |
soc: mediatek: Refactor polling timeout and documentation
Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'drivers/soc/mediatek/mtk-scpsys.c')
-rw-r--r-- | drivers/soc/mediatek/mtk-scpsys.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 503222d0d0da..e97fc0e45400 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -21,7 +21,7 @@ #include <dt-bindings/power/mt8173-power.h> #define MTK_POLL_DELAY_US 10 -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) +#define MTK_POLL_TIMEOUT USEC_PER_SEC #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) @@ -108,6 +108,17 @@ static const char * const clk_names[] = { #define MAX_CLKS 3 +/** + * struct scp_domain_data - scp domain data for power on/off flow + * @name: The domain name. + * @sta_mask: The mask for power on/off status bit. + * @ctl_offs: The offset for main power control register. + * @sram_pdn_bits: The mask for sram power control bits. + * @sram_pdn_ack_bits: The mask for sram power control acked bits. + * @bus_prot_mask: The mask for single step bus protection. + * @clk_id: The basic clocks required by this power domain. + * @caps: The flag for active wake-up action. + */ struct scp_domain_data { const char *name; u32 sta_mask; |