diff options
| author | Lu Baolu <baolu.lu@linux.intel.com> | 2022-05-10 10:34:07 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2022-05-13 15:14:56 +0200 |
| commit | 0d647b33e74f7cb98b7c74d638922d6c03bfdb94 (patch) | |
| tree | 9e09b8d51d4a13c153fac946c689ec1f812355af /drivers | |
| parent | e80552267b63df211c805e8e8c534bfe5909b7e7 (diff) | |
iommu/vt-d: Remove hard coding PGSNP bit in PASID entries
As enforce_cache_coherency has been introduced into the iommu_domain_ops,
the kernel component which owns the iommu domain is able to opt-in its
requirement for force snooping support. The iommu driver has no need to
hard code the page snoop control bit in the PASID table entries anymore.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220508123525.1973626-1-baolu.lu@linux.intel.com
Link: https://lore.kernel.org/r/20220510023407.2759143-9-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/iommu/intel/pasid.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index d19dd66a670c..cb4c1d0cf25c 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -710,9 +710,6 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, pasid_set_fault_enable(pte); pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); - if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED) - pasid_set_pgsnp(pte); - /* * Since it is a second level only translation setup, we should * set SRE bit as well (addresses are expected to be GPAs). |