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authorRajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>2022-10-12 21:58:29 -0400
committerAlex Deucher <alexander.deucher@amd.com>2023-06-09 09:52:28 -0400
commit4482d3c94d7f1d6912521e6de23bb051bfcd084d (patch)
tree05d832073423e4eed1b6f35fd7245fa26487553c /include/drm
parentc1d3f627ff33bf1ae145209030a114c4985beddf (diff)
drm/ttm: add NUMA node id to the pool
This allows backing ttm_tt structure with pages from different NUMA pools. Tested-by: Graham Sider <graham.sider@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/drm')
-rw-r--r--include/drm/ttm/ttm_pool.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/drm/ttm/ttm_pool.h b/include/drm/ttm/ttm_pool.h
index ef09b23d29e3..23bd8be6d4f8 100644
--- a/include/drm/ttm/ttm_pool.h
+++ b/include/drm/ttm/ttm_pool.h
@@ -61,12 +61,14 @@ struct ttm_pool_type {
* struct ttm_pool - Pool for all caching and orders
*
* @dev: the device we allocate pages for
+ * @nid: which numa node to use
* @use_dma_alloc: if coherent DMA allocations should be used
* @use_dma32: if GFP_DMA32 should be used
* @caching: pools for each caching/order
*/
struct ttm_pool {
struct device *dev;
+ int nid;
bool use_dma_alloc;
bool use_dma32;
@@ -81,7 +83,7 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
void ttm_pool_free(struct ttm_pool *pool, struct ttm_tt *tt);
void ttm_pool_init(struct ttm_pool *pool, struct device *dev,
- bool use_dma_alloc, bool use_dma32);
+ int nid, bool use_dma_alloc, bool use_dma32);
void ttm_pool_fini(struct ttm_pool *pool);
int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m);