diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2018-05-08 19:49:46 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-05-18 22:45:01 +0200 |
| commit | a1be3cfdfb81cc55c1b2feb73aca6945f61acddb (patch) | |
| tree | ff7fa5dfaf03aaaf34af0f3dc1b0af105665e763 /include/dt-bindings/memory | |
| parent | 5fd80cf74e1ee06f9895b74d26a3efb01bdad033 (diff) | |
dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions
Tegra114 doesn't have SATA nor PCIe, but TRM seems erroneously document
them.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings/memory')
| -rw-r--r-- | include/dt-bindings/memory/tegra114-mc.h | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h index 54a12adec7b8..dfe99c8a5ba5 100644 --- a/include/dt-bindings/memory/tegra114-mc.h +++ b/include/dt-bindings/memory/tegra114-mc.h @@ -23,23 +23,21 @@ #define TEGRA_SWGROUP_EMUCIF 18 #define TEGRA_SWGROUP_TSEC 19 -#define TEGRA114_MC_RESET_AFI 0 -#define TEGRA114_MC_RESET_AVPC 1 -#define TEGRA114_MC_RESET_DC 2 -#define TEGRA114_MC_RESET_DCB 3 -#define TEGRA114_MC_RESET_EPP 4 -#define TEGRA114_MC_RESET_2D 5 -#define TEGRA114_MC_RESET_HC 6 -#define TEGRA114_MC_RESET_HDA 7 -#define TEGRA114_MC_RESET_ISP 8 -#define TEGRA114_MC_RESET_MPCORE 9 -#define TEGRA114_MC_RESET_MPCORELP 10 -#define TEGRA114_MC_RESET_MPE 11 -#define TEGRA114_MC_RESET_3D 12 -#define TEGRA114_MC_RESET_3D2 13 -#define TEGRA114_MC_RESET_PPCS 14 -#define TEGRA114_MC_RESET_SATA 15 -#define TEGRA114_MC_RESET_VDE 16 -#define TEGRA114_MC_RESET_VI 17 +#define TEGRA114_MC_RESET_AVPC 0 +#define TEGRA114_MC_RESET_DC 1 +#define TEGRA114_MC_RESET_DCB 2 +#define TEGRA114_MC_RESET_EPP 3 +#define TEGRA114_MC_RESET_2D 4 +#define TEGRA114_MC_RESET_HC 5 +#define TEGRA114_MC_RESET_HDA 6 +#define TEGRA114_MC_RESET_ISP 7 +#define TEGRA114_MC_RESET_MPCORE 8 +#define TEGRA114_MC_RESET_MPCORELP 9 +#define TEGRA114_MC_RESET_MPE 10 +#define TEGRA114_MC_RESET_3D 11 +#define TEGRA114_MC_RESET_3D2 12 +#define TEGRA114_MC_RESET_PPCS 13 +#define TEGRA114_MC_RESET_VDE 14 +#define TEGRA114_MC_RESET_VI 15 #endif |