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| author | Artem Bityutskiy <artem.bityutskiy@linux.intel.com> | 2022-03-02 10:16:00 +0200 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2022-03-04 19:54:32 +0100 |
| commit | 3a9cf77b60dc9839b6674943bb7c9dcd524b6294 (patch) | |
| tree | 72b57b5e202ebf70230baceb1bde4ebe9facaee0 /ipc/mqueue.c | |
| parent | da0e58c038e60e7e65d30813ebdfe91687aa8a24 (diff) | |
intel_idle: add core C6 optimization for SPR
Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky Lake
Xeon: if package C6 is disabled, adjust C6 exit latency and target residency to
match core C6 values, instead of using the default package C6 values.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'ipc/mqueue.c')
0 files changed, 0 insertions, 0 deletions