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author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-08-16 11:18:09 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-08-16 11:18:09 -0700 |
commit | 5b179fe052334ea81c9f1841bf782bb0878b61d2 (patch) | |
tree | 177c83587548abb28285df77eb8acac25611b568 /rust | |
parent | 4a621e291000c3756c353c5671ade4837ba68e3e (diff) | |
parent | 32d5f7add080a936e28ab4142bfeea6b06999789 (diff) |
Merge tag 'riscv-for-linus-6.11-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
- reintroduce the text patching global icache flush
- fix syscall entry code to correctly initialize a0, which manifested
as a strace bug
- XIP kernels now map the entire kernel, which fixes boot under at
least DEBUG_VIRTUAL=y
- initialize all nodes in the acpi_early_node_map initializer
- fix OOB access in the Andes vendor extension probing code
- A new key for scalar misaligned access performance in hwprobe, which
correctly treat the values as an enum (as opposed to a bitmap)
* tag 'riscv-for-linus-6.11-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Fix out-of-bounds when accessing Andes per hart vendor extension array
RISC-V: hwprobe: Add SCALAR to misaligned perf defines
RISC-V: hwprobe: Add MISALIGNED_PERF key
RISC-V: ACPI: NUMA: initialize all values of acpi_early_node_map to NUMA_NO_NODE
riscv: change XIP's kernel_map.size to be size of the entire kernel
riscv: entry: always initialize regs->a0 to -ENOSYS
riscv: Re-introduce global icache flush in patch_text_XXX()
Diffstat (limited to 'rust')
0 files changed, 0 insertions, 0 deletions