ASoC: mt8365: Fix -Werror builds

Merge series from Mark Brown <broonie@kernel.org>:

Nathan reported that the newly added mt8365 drivers were causing a
number of warnings which break -Werror builds, these were only visible
on arm64 since the drivers did not have COMPILE_TEST enabled.  Fix this
and some other minor stuff I noticed while doing so.

8 files changed, 120 insertions, 153 deletions

diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index e6f7a5a49794..3033e2d3fe16 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -301,7 +301,7 @@ config SND_SOC_MT8195_MT6359
 
 config SND_SOC_MT8365
 	tristate "ASoC support for MediaTek MT8365 chip"
-	depends on ARCH_MEDIATEK
+	depends on ARCH_MEDIATEK || COMPILE_TEST
 	select SND_SOC_MEDIATEK
 	help
 	  This adds ASoC platform driver support for MediaTek MT8365 chip
diff --git a/sound/soc/mediatek/mt8365/mt8365-afe-clk.c b/sound/soc/mediatek/mt8365/mt8365-afe-clk.c
index 300d1f0ae660..8a0af2ea8546 100644
--- a/sound/soc/mediatek/mt8365/mt8365-afe-clk.c
+++ b/sound/soc/mediatek/mt8365/mt8365-afe-clk.c
@@ -295,7 +295,7 @@ int mt8365_afe_disable_afe_on(struct mtk_base_afe *afe)
 	return 0;
 }
 
-int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
+static int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
 {
 	if (apll1)
 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
@@ -307,7 +307,7 @@ int mt8365_afe_hd_engen_enable(struct mtk_base_afe *afe, bool apll1)
 	return 0;
 }
 
-int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
+static int mt8365_afe_hd_engen_disable(struct mtk_base_afe *afe, bool apll1)
 {
 	if (apll1)
 		regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
diff --git a/sound/soc/mediatek/mt8365/mt8365-afe-common.h b/sound/soc/mediatek/mt8365/mt8365-afe-common.h
index 1fa87e54a57f..731406e15ac7 100644
--- a/sound/soc/mediatek/mt8365/mt8365-afe-common.h
+++ b/sound/soc/mediatek/mt8365/mt8365-afe-common.h
@@ -421,7 +421,6 @@ static inline u32 AutoRstThLo(unsigned int fs)
 	}
 }
 
-bool mt8365_afe_clk_group_48k(int sample_rate);
 bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id);
 bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id);
 
diff --git a/sound/soc/mediatek/mt8365/mt8365-afe-pcm.c b/sound/soc/mediatek/mt8365/mt8365-afe-pcm.c
index 6ca10e2046c8..743b46572144 100644
--- a/sound/soc/mediatek/mt8365/mt8365-afe-pcm.c
+++ b/sound/soc/mediatek/mt8365/mt8365-afe-pcm.c
@@ -170,7 +170,7 @@ bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id)
 	return false;
 }
 
-bool mt8365_afe_clk_group_44k(int sample_rate)
+static bool mt8365_afe_clk_group_44k(int sample_rate)
 {
 	if (sample_rate == 11025 ||
 	    sample_rate == 22050 ||
@@ -182,7 +182,7 @@ bool mt8365_afe_clk_group_44k(int sample_rate)
 		return false;
 }
 
-bool mt8365_afe_clk_group_48k(int sample_rate)
+static bool mt8365_afe_clk_group_48k(int sample_rate)
 {
 	return (!mt8365_afe_clk_group_44k(sample_rate));
 }
@@ -496,8 +496,8 @@ static int mt8365_afe_configure_cm(struct mtk_base_afe *afe,
 	return 0;
 }
 
-int mt8365_afe_fe_startup(struct snd_pcm_substream *substream,
-			  struct snd_soc_dai *dai)
+static int mt8365_afe_fe_startup(struct snd_pcm_substream *substream,
+				 struct snd_soc_dai *dai)
 {
 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
@@ -651,7 +651,6 @@ static int mt8365_afe_fe_hw_free(struct snd_pcm_substream *substream,
 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
 	struct mt8365_afe_private *afe_priv = afe->platform_priv;
 	int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id;
-	struct mtk_base_afe_memif *memif = &afe->memif[dai_id];
 	struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id];
 	int ret = 0;
 
@@ -714,8 +713,8 @@ static int mt8365_afe_fe_prepare(struct snd_pcm_substream *substream,
 	return 0;
 }
 
-int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
-			  struct snd_soc_dai *dai)
+static int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
+				 struct snd_soc_dai *dai)
 {
 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
diff --git a/sound/soc/mediatek/mt8365/mt8365-dai-dmic.c b/sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
index a3bf54751420..f9945c2a2cd1 100644
--- a/sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
+++ b/sound/soc/mediatek/mt8365/mt8365-dai-dmic.c
@@ -108,36 +108,6 @@ static void mt8365_dai_disable_dmic(struct mtk_base_afe *afe,
 	regmap_update_bits(afe->regmap, reg, mask, 0);
 }
 
-static const struct reg_sequence mt8365_dmic_iir_coeff[] = {
-	{ AFE_DMIC0_IIR_COEF_02_01, 0x00000000 },
-	{ AFE_DMIC0_IIR_COEF_04_03, 0x00003FB8 },
-	{ AFE_DMIC0_IIR_COEF_06_05, 0x3FB80000 },
-	{ AFE_DMIC0_IIR_COEF_08_07, 0x3FB80000 },
-	{ AFE_DMIC0_IIR_COEF_10_09, 0x0000C048 },
-	{ AFE_DMIC1_IIR_COEF_02_01, 0x00000000 },
-	{ AFE_DMIC1_IIR_COEF_04_03, 0x00003FB8 },
-	{ AFE_DMIC1_IIR_COEF_06_05, 0x3FB80000 },
-	{ AFE_DMIC1_IIR_COEF_08_07, 0x3FB80000 },
-	{ AFE_DMIC1_IIR_COEF_10_09, 0x0000C048 },
-	{ AFE_DMIC2_IIR_COEF_02_01, 0x00000000 },
-	{ AFE_DMIC2_IIR_COEF_04_03, 0x00003FB8 },
-	{ AFE_DMIC2_IIR_COEF_06_05, 0x3FB80000 },
-	{ AFE_DMIC2_IIR_COEF_08_07, 0x3FB80000 },
-	{ AFE_DMIC2_IIR_COEF_10_09, 0x0000C048 },
-	{ AFE_DMIC3_IIR_COEF_02_01, 0x00000000 },
-	{ AFE_DMIC3_IIR_COEF_04_03, 0x00003FB8 },
-	{ AFE_DMIC3_IIR_COEF_06_05, 0x3FB80000 },
-	{ AFE_DMIC3_IIR_COEF_08_07, 0x3FB80000 },
-	{ AFE_DMIC3_IIR_COEF_10_09, 0x0000C048 },
-};
-
-static int mt8365_dai_load_dmic_iir_coeff_table(struct mtk_base_afe *afe)
-{
-	return regmap_multi_reg_write(afe->regmap,
-				      mt8365_dmic_iir_coeff,
-				      ARRAY_SIZE(mt8365_dmic_iir_coeff));
-}
-
 static int mt8365_dai_configure_dmic(struct mtk_base_afe *afe,
 				     struct snd_pcm_substream *substream,
 				     struct snd_soc_dai *dai)
diff --git a/sound/soc/mediatek/mt8365/mt8365-dai-i2s.c b/sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
index b4d4d6705c86..3482d8f8b4e7 100644
--- a/sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
+++ b/sound/soc/mediatek/mt8365/mt8365-dai-i2s.c
@@ -385,7 +385,7 @@ static int mt8365_afe_set_2nd_i2s_asrc(struct mtk_base_afe *afe,
 		/* disable IIR coeff SRAM access */
 		regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
 				   COEFF_SRAM_CTRL,
-				   (unsigned long)~COEFF_SRAM_CTRL);
+				   ~COEFF_SRAM_CTRL);
 		regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
 				   CLR_IIR_HISTORY | IIR_EN | IIR_STAGE_MASK,
 				   CLR_IIR_HISTORY | IIR_EN |
@@ -393,7 +393,7 @@ static int mt8365_afe_set_2nd_i2s_asrc(struct mtk_base_afe *afe,
 	} else {
 		/* disable IIR */
 		regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON2,
-				   IIR_EN, (unsigned long)~IIR_EN);
+				   IIR_EN, ~IIR_EN);
 	}
 
 	/* CON3 setting (RX OFS) */
@@ -456,7 +456,7 @@ static int mt8365_afe_set_2nd_i2s_asrc_enable(struct mtk_base_afe *afe,
 				   ASM_ON, ASM_ON);
 	else
 		regmap_update_bits(afe->regmap, AFE_ASRC_2CH_CON0,
-				   ASM_ON, (unsigned long)~ASM_ON);
+				   ASM_ON, ~ASM_ON);
 	return 0;
 }
 
diff --git a/sound/soc/mediatek/mt8365/mt8365-mt6357.c b/sound/soc/mediatek/mt8365/mt8365-mt6357.c
index fef76118f801..1b8d1656101b 100644
--- a/sound/soc/mediatek/mt8365/mt8365-mt6357.c
+++ b/sound/soc/mediatek/mt8365/mt8365-mt6357.c
@@ -290,9 +290,8 @@ static int mt8365_mt6357_dev_probe(struct mtk_soc_card_data *soc_card_data, bool
 	struct mtk_platform_card_data *card_data = soc_card_data->card_data;
 	struct snd_soc_card *card = card_data->card;
 	struct device *dev = card->dev;
-	struct device_node *platform_node;
 	struct mt8365_mt6357_priv *mach_priv;
-	int i, ret;
+	int ret;
 
 	card->dev = dev;
 	ret = parse_dai_link_info(card);
diff --git a/sound/soc/mediatek/mt8365/mt8365-reg.h b/sound/soc/mediatek/mt8365/mt8365-reg.h
index 1051718c29f3..4ebbb94ff02e 100644
--- a/sound/soc/mediatek/mt8365/mt8365-reg.h
+++ b/sound/soc/mediatek/mt8365/mt8365-reg.h
@@ -736,57 +736,57 @@
 #define AFE_IRQ_STATUS_BITS		0x3ff
 
 /* AUDIO_TOP_CON0 (0x0000) */
-#define AUD_TCON0_PDN_TML		BIT(27)
-#define AUD_TCON0_PDN_DAC_PREDIS	BIT(26)
-#define AUD_TCON0_PDN_DAC		BIT(25)
-#define AUD_TCON0_PDN_ADC		BIT(24)
-#define AUD_TCON0_PDN_TDM_IN		BIT(23)
-#define AUD_TCON0_PDN_TDM_OUT		BIT(22)
-#define AUD_TCON0_PDN_SPDIF		BIT(21)
-#define AUD_TCON0_PDN_APLL_TUNER	BIT(19)
-#define AUD_TCON0_PDN_APLL2_TUNER	BIT(18)
-#define AUD_TCON0_PDN_INTDIR		BIT(15)
-#define AUD_TCON0_PDN_24M		BIT(9)
-#define AUD_TCON0_PDN_22M		BIT(8)
-#define AUD_TCON0_PDN_I2S_IN		BIT(6)
-#define AUD_TCON0_PDN_AFE		BIT(2)
+#define AUD_TCON0_PDN_TML		(1U << 27)
+#define AUD_TCON0_PDN_DAC_PREDIS	(1U << 26)
+#define AUD_TCON0_PDN_DAC		(1U << 25)
+#define AUD_TCON0_PDN_ADC		(1U << 24)
+#define AUD_TCON0_PDN_TDM_IN		(1U << 23)
+#define AUD_TCON0_PDN_TDM_OUT		(1U << 22)
+#define AUD_TCON0_PDN_SPDIF		(1U << 21)
+#define AUD_TCON0_PDN_APLL_TUNER	(1U << 19)
+#define AUD_TCON0_PDN_APLL2_TUNER	(1U << 18)
+#define AUD_TCON0_PDN_INTDIR		(1U << 15)
+#define AUD_TCON0_PDN_24M		(1U << 9)
+#define AUD_TCON0_PDN_22M		(1U << 8)
+#define AUD_TCON0_PDN_I2S_IN		(1U << 6)
+#define AUD_TCON0_PDN_AFE		(1U << 2)
 
 /* AUDIO_TOP_CON1 (0x0004) */
-#define AUD_TCON1_PDN_TDM_ASRC		BIT(15)
-#define AUD_TCON1_PDN_GENERAL2_ASRC	BIT(14)
-#define AUD_TCON1_PDN_GENERAL1_ASRC	BIT(13)
-#define AUD_TCON1_PDN_CONNSYS_I2S_ASRC	BIT(12)
-#define AUD_TCON1_PDN_DMIC3_ADC		BIT(11)
-#define AUD_TCON1_PDN_DMIC2_ADC		BIT(10)
-#define AUD_TCON1_PDN_DMIC1_ADC		BIT(9)
-#define AUD_TCON1_PDN_DMIC0_ADC		BIT(8)
-#define AUD_TCON1_PDN_I2S4_BCLK		BIT(7)
-#define AUD_TCON1_PDN_I2S3_BCLK		BIT(6)
-#define AUD_TCON1_PDN_I2S2_BCLK		BIT(5)
-#define AUD_TCON1_PDN_I2S1_BCLK		BIT(4)
+#define AUD_TCON1_PDN_TDM_ASRC		(1U << 15)
+#define AUD_TCON1_PDN_GENERAL2_ASRC	(1U << 14)
+#define AUD_TCON1_PDN_GENERAL1_ASRC	(1U << 13)
+#define AUD_TCON1_PDN_CONNSYS_I2S_ASRC	(1U << 12)
+#define AUD_TCON1_PDN_DMIC3_ADC		(1U << 11)
+#define AUD_TCON1_PDN_DMIC2_ADC		(1U << 10)
+#define AUD_TCON1_PDN_DMIC1_ADC		(1U << 9)
+#define AUD_TCON1_PDN_DMIC0_ADC		(1U << 8)
+#define AUD_TCON1_PDN_I2S4_BCLK		(1U << 7)
+#define AUD_TCON1_PDN_I2S3_BCLK		(1U << 6)
+#define AUD_TCON1_PDN_I2S2_BCLK		(1U << 5)
+#define AUD_TCON1_PDN_I2S1_BCLK		(1U << 4)
 
 /* AUDIO_TOP_CON3 (0x000C) */
-#define AUD_TCON3_HDMI_BCK_INV		BIT(3)
+#define AUD_TCON3_HDMI_BCK_INV		(1U << 3)
 
 /* AFE_I2S_CON (0x0018) */
-#define AFE_I2S_CON_PHASE_SHIFT_FIX	BIT(31)
-#define AFE_I2S_CON_FROM_IO_MUX		BIT(28)
-#define AFE_I2S_CON_LOW_JITTER_CLK	BIT(12)
+#define AFE_I2S_CON_PHASE_SHIFT_FIX	(1U << 31)
+#define AFE_I2S_CON_FROM_IO_MUX		(1U << 28)
+#define AFE_I2S_CON_LOW_JITTER_CLK	(1U << 12)
 #define AFE_I2S_CON_RATE_MASK		GENMASK(11, 8)
-#define AFE_I2S_CON_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON_SRC_SLAVE		BIT(2)
+#define AFE_I2S_CON_FORMAT_I2S		(1U << 3)
+#define AFE_I2S_CON_SRC_SLAVE		(1U << 2)
 
 /* AFE_ASRC_2CH_CON0 */
-#define ONE_HEART	BIT(31)
-#define CHSET_STR_CLR	BIT(4)
-#define COEFF_SRAM_CTRL	BIT(1)
-#define ASM_ON		BIT(0)
+#define ONE_HEART	(1U << 31)
+#define CHSET_STR_CLR	(1U << 4)
+#define COEFF_SRAM_CTRL	(1U << 1)
+#define ASM_ON		(1U << 0)
 
 /* CON2 */
-#define O16BIT		BIT(19)
-#define CLR_IIR_HISTORY	BIT(17)
-#define IS_MONO		BIT(16)
-#define IIR_EN		BIT(11)
+#define O16BIT		(1U << 19)
+#define CLR_IIR_HISTORY	(1U << 17)
+#define IS_MONO		(1U << 16)
+#define IIR_EN		(1U << 11)
 #define IIR_STAGE_MASK	GENMASK(10, 8)
 
 /* CON5 */
@@ -795,80 +795,80 @@
 #define CALI_96_CYCLE	FIELD_PREP(CALI_CYCLE_MASK, 0x5F)
 #define CALI_441_CYCLE	FIELD_PREP(CALI_CYCLE_MASK, 0x1B8)
 
-#define CALI_AUTORST	BIT(15)
-#define AUTO_TUNE_FREQ5	BIT(12)
-#define COMP_FREQ_RES	BIT(11)
+#define CALI_AUTORST	(1U << 15)
+#define AUTO_TUNE_FREQ5	(1U << 12)
+#define COMP_FREQ_RES	(1U << 11)
 
 #define CALI_SEL_MASK	GENMASK(9, 8)
 #define CALI_SEL_00	FIELD_PREP(CALI_SEL_MASK, 0)
 #define CALI_SEL_01	FIELD_PREP(CALI_SEL_MASK, 1)
 
-#define CALI_BP_DGL		BIT(7) /* Bypass the deglitch circuit */
-#define AUTO_TUNE_FREQ4		BIT(3)
-#define CALI_AUTO_RESTART	BIT(2)
-#define CALI_USE_FREQ_OUT	BIT(1)
-#define CALI_ON			BIT(0)
+#define CALI_BP_DGL		(1U << 7) /* Bypass the deglitch circuit */
+#define AUTO_TUNE_FREQ4		(1U << 3)
+#define CALI_AUTO_RESTART	(1U << 2)
+#define CALI_USE_FREQ_OUT	(1U << 1)
+#define CALI_ON			(1U << 0)
 
-#define AFE_I2S_CON_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON_EN			BIT(0)
+#define AFE_I2S_CON_WLEN_32BIT		(1U << 1)
+#define AFE_I2S_CON_EN			(1U << 0)
 
-#define AFE_CONN3_I03_O03_S		BIT(3)
-#define AFE_CONN4_I04_O04_S		BIT(4)
-#define AFE_CONN4_I03_O04_S		BIT(3)
+#define AFE_CONN3_I03_O03_S		(1U << 3)
+#define AFE_CONN4_I04_O04_S		(1U << 4)
+#define AFE_CONN4_I03_O04_S		(1U << 3)
 
 /* AFE_I2S_CON1 (0x0034) */
-#define AFE_I2S_CON1_I2S2_TO_PAD	BIT(18)
+#define AFE_I2S_CON1_I2S2_TO_PAD	(1U << 18)
 #define AFE_I2S_CON1_TDMOUT_TO_PAD	(0 << 18)
 #define AFE_I2S_CON1_RATE		GENMASK(11, 8)
-#define AFE_I2S_CON1_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON1_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON1_EN			BIT(0)
+#define AFE_I2S_CON1_FORMAT_I2S		(1U << 3)
+#define AFE_I2S_CON1_WLEN_32BIT		(1U << 1)
+#define AFE_I2S_CON1_EN			(1U << 0)
 
 /* AFE_I2S_CON2 (0x0038) */
-#define AFE_I2S_CON2_LOW_JITTER_CLK	BIT(12)
+#define AFE_I2S_CON2_LOW_JITTER_CLK	(1U << 12)
 #define AFE_I2S_CON2_RATE		GENMASK(11, 8)
-#define AFE_I2S_CON2_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON2_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON2_EN			BIT(0)
+#define AFE_I2S_CON2_FORMAT_I2S		(1U << 3)
+#define AFE_I2S_CON2_WLEN_32BIT		(1U << 1)
+#define AFE_I2S_CON2_EN			(1U << 0)
 
 /* AFE_I2S_CON3 (0x004C) */
-#define AFE_I2S_CON3_LOW_JITTER_CLK	BIT(12)
+#define AFE_I2S_CON3_LOW_JITTER_CLK	(1U << 12)
 #define AFE_I2S_CON3_RATE		GENMASK(11, 8)
-#define AFE_I2S_CON3_FORMAT_I2S		BIT(3)
-#define AFE_I2S_CON3_WLEN_32BIT		BIT(1)
-#define AFE_I2S_CON3_EN			BIT(0)
+#define AFE_I2S_CON3_FORMAT_I2S		(1U << 3)
+#define AFE_I2S_CON3_WLEN_32BIT		(1U << 1)
+#define AFE_I2S_CON3_EN			(1U << 0)
 
 /* AFE_ADDA_DL_SRC2_CON0 (0x0108) */
 #define AFE_ADDA_DL_SAMPLING_RATE	GENMASK(31, 28)
 #define AFE_ADDA_DL_8X_UPSAMPLE		GENMASK(25, 24)
-#define AFE_ADDA_DL_MUTE_OFF_CH1	BIT(12)
-#define AFE_ADDA_DL_MUTE_OFF_CH2	BIT(11)
-#define AFE_ADDA_DL_VOICE_DATA		BIT(5)
-#define AFE_ADDA_DL_DEGRADE_GAIN	BIT(1)
+#define AFE_ADDA_DL_MUTE_OFF_CH1	(1U << 12)
+#define AFE_ADDA_DL_MUTE_OFF_CH2	(1U << 11)
+#define AFE_ADDA_DL_VOICE_DATA		(1U << 5)
+#define AFE_ADDA_DL_DEGRADE_GAIN	(1U << 1)
 
 /* AFE_ADDA_UL_SRC_CON0 (0x0114) */
 #define AFE_ADDA_UL_SAMPLING_RATE	GENMASK(19, 17)
 
 /* AFE_ADDA_UL_DL_CON0 */
-#define AFE_ADDA_UL_DL_ADDA_AFE_ON	BIT(0)
-#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON	BIT(1)
+#define AFE_ADDA_UL_DL_ADDA_AFE_ON	(1U << 0)
+#define AFE_ADDA_UL_DL_DMIC_CLKDIV_ON	(1U << 1)
 
 /* AFE_APLL_TUNER_CFG (0x03f0) */
 #define AFE_APLL_TUNER_CFG_MASK		GENMASK(15, 1)
-#define AFE_APLL_TUNER_CFG_EN_MASK	BIT(0)
+#define AFE_APLL_TUNER_CFG_EN_MASK	(1U << 0)
 
 /* AFE_APLL_TUNER_CFG1 (0x03f4) */
 #define AFE_APLL_TUNER_CFG1_MASK	GENMASK(15, 1)
-#define AFE_APLL_TUNER_CFG1_EN_MASK	BIT(0)
+#define AFE_APLL_TUNER_CFG1_EN_MASK	(1U << 0)
 
 /* PCM_INTF_CON1 (0x0550) */
-#define PCM_INTF_CON1_EXT_MODEM		BIT(17)
+#define PCM_INTF_CON1_EXT_MODEM		(1U << 17)
 #define PCM_INTF_CON1_16BIT		(0 << 16)
-#define PCM_INTF_CON1_24BIT		BIT(16)
+#define PCM_INTF_CON1_24BIT		(1U << 16)
 #define PCM_INTF_CON1_32BCK		(0 << 14)
-#define PCM_INTF_CON1_64BCK		BIT(14)
+#define PCM_INTF_CON1_64BCK		(1U << 14)
 #define PCM_INTF_CON1_MASTER_MODE	(0 << 5)
-#define PCM_INTF_CON1_SLAVE_MODE	BIT(5)
+#define PCM_INTF_CON1_SLAVE_MODE	(1U << 5)
 #define PCM_INTF_CON1_FS_MASK		GENMASK(4, 3)
 #define PCM_INTF_CON1_FS_8K		FIELD_PREP(PCM_INTF_CON1_FS_MASK, 0)
 #define PCM_INTF_CON1_FS_16K		FIELD_PREP(PCM_INTF_CON1_FS_MASK, 1)
@@ -877,12 +877,12 @@
 #define PCM_INTF_CON1_SYNC_LEN_MASK	GENMASK(13, 9)
 #define PCM_INTF_CON1_SYNC_LEN(x)	FIELD_PREP(PCM_INTF_CON1_SYNC_LEN_MASK, ((x) - 1))
 #define PCM_INTF_CON1_FORMAT_MASK	GENMASK(2, 1)
-#define PCM_INTF_CON1_SYNC_OUT_INV	BIT(23)
-#define PCM_INTF_CON1_BCLK_OUT_INV	BIT(22)
-#define PCM_INTF_CON1_SYNC_IN_INV	BIT(21)
-#define PCM_INTF_CON1_BCLK_IN_INV	BIT(20)
-#define PCM_INTF_CON1_BYPASS_ASRC	BIT(6)
-#define PCM_INTF_CON1_EN		BIT(0)
+#define PCM_INTF_CON1_SYNC_OUT_INV	(1U << 23)
+#define PCM_INTF_CON1_BCLK_OUT_INV	(1U << 22)
+#define PCM_INTF_CON1_SYNC_IN_INV	(1U << 21)
+#define PCM_INTF_CON1_BCLK_IN_INV	(1U << 20)
+#define PCM_INTF_CON1_BYPASS_ASRC	(1U << 6)
+#define PCM_INTF_CON1_EN		(1U << 0)
 #define PCM_INTF_CON1_CONFIG_MASK	(0xf3fffe)
 
 /* AFE_DMIC0_UL_SRC_CON0 (0x05b4)
@@ -892,9 +892,9 @@
  */
 #define DMIC_TOP_CON_CK_PHASE_SEL_CH1		GENMASK(29, 27)
 #define DMIC_TOP_CON_CK_PHASE_SEL_CH2		GENMASK(26, 24)
-#define DMIC_TOP_CON_TWO_WIRE_MODE		BIT(23)
-#define DMIC_TOP_CON_CH2_ON			BIT(22)
-#define DMIC_TOP_CON_CH1_ON			BIT(21)
+#define DMIC_TOP_CON_TWO_WIRE_MODE		(1U << 23)
+#define DMIC_TOP_CON_CH2_ON			(1U << 22)
+#define DMIC_TOP_CON_CH1_ON			(1U << 21)
 #define DMIC_TOP_CON_VOICE_MODE_MASK		GENMASK(19, 17)
 #define DMIC_TOP_CON_VOICE_MODE_8K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 0)
 #define DMIC_TOP_CON_VOICE_MODE_16K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 1)
@@ -902,28 +902,28 @@
 #define DMIC_TOP_CON_VOICE_MODE_48K		FIELD_PREP(DMIC_TOP_CON_VOICE_MODE_MASK, 3)
 #define DMIC_TOP_CON_LOW_POWER_MODE_MASK	GENMASK(15, 14)
 #define DMIC_TOP_CON_LOW_POWER_MODE(x)		FIELD_PREP(DMIC_TOP_CON_LOW_POWER_MODE_MASK, (x))
-#define DMIC_TOP_CON_IIR_ON			BIT(10)
+#define DMIC_TOP_CON_IIR_ON			(1U << 10)
 #define DMIC_TOP_CON_IIR_MODE			GENMASK(9, 7)
-#define DMIC_TOP_CON_INPUT_MODE			BIT(5)
-#define DMIC_TOP_CON_SDM3_LEVEL_MODE		BIT(1)
-#define DMIC_TOP_CON_SRC_ON			BIT(0)
+#define DMIC_TOP_CON_INPUT_MODE			(1U << 5)
+#define DMIC_TOP_CON_SDM3_LEVEL_MODE		(1U << 1)
+#define DMIC_TOP_CON_SRC_ON			(1U << 0)
 #define DMIC_TOP_CON_SDM3_DE_SELECT		(0 << 1)
 #define DMIC_TOP_CON_CONFIG_MASK		(0x3f8ed7a6)
 
 /* AFE_CONN_24BIT (0x0AA4) */
-#define AFE_CONN_24BIT_O10		BIT(10)
-#define AFE_CONN_24BIT_O09		BIT(9)
-#define AFE_CONN_24BIT_O06		BIT(6)
-#define AFE_CONN_24BIT_O05		BIT(5)
-#define AFE_CONN_24BIT_O04		BIT(4)
-#define AFE_CONN_24BIT_O03		BIT(3)
-#define AFE_CONN_24BIT_O02		BIT(2)
-#define AFE_CONN_24BIT_O01		BIT(1)
-#define AFE_CONN_24BIT_O00		BIT(0)
+#define AFE_CONN_24BIT_O10		(1U << 10)
+#define AFE_CONN_24BIT_O09		(1U << 9)
+#define AFE_CONN_24BIT_O06		(1U << 6)
+#define AFE_CONN_24BIT_O05		(1U << 5)
+#define AFE_CONN_24BIT_O04		(1U << 4)
+#define AFE_CONN_24BIT_O03		(1U << 3)
+#define AFE_CONN_24BIT_O02		(1U << 2)
+#define AFE_CONN_24BIT_O01		(1U << 1)
+#define AFE_CONN_24BIT_O00		(1U << 0)
 
 /* AFE_HD_ENGEN_ENABLE */
-#define AFE_22M_PLL_EN		BIT(0)
-#define AFE_24M_PLL_EN		BIT(1)
+#define AFE_22M_PLL_EN		(1U << 0)
+#define AFE_24M_PLL_EN		(1U << 1)
 
 /* AFE_GAIN1_CON0 (0x0410) */
 #define AFE_GAIN1_CON0_EN_MASK			GENMASK(0, 0)
@@ -940,15 +940,15 @@
 /* AFE_CM2_CON0 (0x0e60) */
 #define CM_AFE_CM_CH_NUM_MASK		GENMASK(3, 0)
 #define CM_AFE_CM_CH_NUM(x)		FIELD_PREP(CM_AFE_CM_CH_NUM_MASK, ((x) - 1))
-#define CM_AFE_CM_ON			BIT(4)
+#define CM_AFE_CM_ON			(1U << 4)
 #define CM_AFE_CM_START_DATA_MASK	GENMASK(11, 8)
 
-#define CM_AFE_CM1_VUL_SEL		BIT(12)
+#define CM_AFE_CM1_VUL_SEL		(1U << 12)
 #define CM_AFE_CM1_IN_MODE_MASK		GENMASK(19, 16)
-#define CM_AFE_CM2_TDM_SEL		BIT(12)
-#define CM_AFE_CM2_CLK_SEL		BIT(13)
-#define CM_AFE_CM2_GASRC1_OUT_SEL	BIT(17)
-#define CM_AFE_CM2_GASRC2_OUT_SEL	BIT(16)
+#define CM_AFE_CM2_TDM_SEL		(1U << 12)
+#define CM_AFE_CM2_CLK_SEL		(1U << 13)
+#define CM_AFE_CM2_GASRC1_OUT_SEL	(1U << 17)
+#define CM_AFE_CM2_GASRC2_OUT_SEL	(1U << 16)
 
 /* AFE_CM2_CONN* */
 #define CM2_AFE_CM2_CONN_CFG1(x)	FIELD_PREP(CM2_AFE_CM2_CONN_CFG1_MASK, (x))